Welcome to the www.nammavlsi.com Interactive Verilog Tutorial.
Whether you are an experienced programmer or not, this website is intended for everyone who wishes to learn the Verilog programming language. Just click on the chapter you wish to begin from, and follow the instructions. Good luck!
After you have a thorough understanding of digital design principles, we will explore the syntax and semantics of Verilog. You’ll discover how to write Verilog code effectively, exploring data types, operators, and modules. We will lead you through both structural and behavioral modeling styles, instructing you on how to describe the structure and behavior of digital circuits.
To enhance your learning, we will provide you with a variety of examples and exercises.
You will be taught how to simulate your Verilog designs, analyze their results, and verify their correctness and functionality. We will learn about various verification methods, including test benches, and provide guidance on how to validate your designs in an effective manner.
Verilog Index:
- Introduction to Verilog
- Levels of Design Description in Verilog
- MODULE in Verilog
- Language Constructs & Conventions
- Numbers, Strings, Logic, Data Types & Operators
- Gate Level Modelling in Verilog
- Gate Level — Arrays, Flip-Flops, Delays, Strengths & Nets
- Modelling at Data Flow Level
- Behavioral Modelling — Part 1
- Behavioral Modelling — Part 2
- Behavioral Modelling — Part 3
- Behavioral Modelling — Part 4
- Switch Level Modelling
- Switch Level — Delays, Strengths & Trireg
- System Tasks, Functions & Compiler Directives
- System Tasks, Functions & File I/O
- Compiler Directives, Hierarchical Access & UDPs
Verilog Designs with Testbenches
- Half Adder
- 1-bit Full Adder
- 1-bit Full Adder using Half Adder
- 4-bit Full adder using Half Adder
- Mux using Case statement
- Mux using logical expression
- Mux using Conditional operator
- ALU
- D Flip-Flop with synchronous reset
- D Flip-Flop with Asynchronous reset
- Sequence Detector using Mealy machine (1101, Non-overlapping)
- Sequence Detector using Moore machine (1101, Non-Overlapping)
- Sequence Detector using Mealy machine (1101, Overlapping)
- Sequence Detector using Moore machine (1101, Overlapping)
- Count the Number of 1's
- Binary to Gray Conversion
- Up Down Counter
- Random Counter
- Clock Divider
- PIPO
- N-bit Universal Shift Register
- 4 bit LSFR
- Single port RAM (128x8)
- Dual port RAM (128x8)
- Synchronous FIFO
- Asynchronous FIFO
- 8x8 Sequential Multiplier
- 64 bit Pipelined Multiplier