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What this series covers. Gate-Level Simulation is the simulation of a synthesised netlist — with or without timing — to verify that the RTL-to-gate translation has not broken functional intent, and that real propagation delays do not violate timing constraints. This series walks through every layer: why GLS exists alongside STA and equivalence checking, how the three simulation modes work (zero delay, unit delay, SDF), how delays are modelled and annotated, how to set up an Xcelium GLS run from scratch, how to selectively disable timing checks, and how to diagnose and fix the most common GLS failures. Every article connects tool knowledge to the underlying circuit and architecture concepts — so you understand why each switch or warning exists, not just how to use it.
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Prerequisites. Digital Electronics series (DE-01 through DE-12) and Computer Architecture series (CA-01 through CA-12) are recommended — particularly combinational and sequential logic (CA-12 / DE-05 through DE-08), RTL simulation concepts, and basic VLSI flow awareness. Familiarity with SystemVerilog or Verilog syntax at the module/port level is assumed throughout.
GLS-01
What gate-level simulation is and how it differs from RTL simulation. Why STA and equivalence checking alone are insufficient — asynchronous interfaces, glitches on edge-sensitive signals, DFT verification after scan insertion, power-up and reset verification, X-state pessimism, and clock-tree synthesis checks. GLS role in the verification signoff flow. The GLS loop: netlist → regression → debug → signoff.
Concept
Flow
VLSI Link
GLS-02
The three GLS simulation modes: zero delay (functionality only, fast, nospecify switch), unit delay (uniform 1-time-unit delays, race condition detection), and SDF simulation (back-annotated actual delays from synthesis/P&R/STA tools). Transport delay vs inertial delay models — what each means physically, when each is used. Pulse rejection and the PULSE_E / PULSE_R switches. Xcelium default behaviour and how to override it.
Concept
Hardware
Diagram
VLSI Link
GLS-03
What an SDF (Standard Delay Format) file contains — header fields (SDFVERSION, DESIGN, VENDOR, TIMESCALE, VOLTAGE, TEMPERATURE), cell entries, IOPATH delays, and timing checks. Two annotation methods: $sdf_annotate system task (elaboration-time, runs at time 0) and the -sdf_cmd_file command-line option (higher precedence). Back-annotation scope, MTM control (MIN/TYP/MAX), scale factors, and reading the SDF annotation statistics log. Compiled SDF (.sdf.X) generation via xmsdfc.
Concept
Flow
VLSI Link
GLS-04
Three strategies for disabling timing checks at different granularities. Global switches at elaboration: -NOSPECIFY, -NOTIMINGCHECKS, -NONOTIFIER, -NO_TCHK_MSG, -NTCNOTCHKS — what each disables and when to use it. Local control via timing files (-tfile): DEFAULT, BASENAME, PATH, CELLINST, CELLLIB, and INCLUDE keywords with worked examples. Runtime disable via the tcheck command (tcheck instance_path -off/-on). $setuphold vs $setup/$hold asymmetry in tfile. The RETAIN SDF keyword and -sdf_ignore_retain.
Concept
Flow
Debug
GLS-05
Step-by-step GLS flow setup using a counter example. Required inputs: gate-level netlist, library cell Verilog models, SDF file, testbench. Running zero delay simulation: xrun with -nospecify, reading the SDFSKPA warning, understanding what is and isn’t active. Running SDF simulation: xrun with -sdf_cmd_file or $sdf_annotate, reading the SDF statistics output (path delays, $setuphold, $recovery, $removal, $hold, $width annotation percentages). Using -sdf_verbose and -sdfstats for debug. The GLS regression loop: run → debug → new netlist/SDF → re-run → signoff.
Flow
Diagram
VLSI Link
GLS-06
Issue 1: Debugging zero-delay gate oscillation (TRZDGOC warning) — using -gateloopwarn and -access +c, the drivers -active TCL command, adding delays to break loops, seq_udp_delay and -sequdp_nba_delay switches. Issue 2: CUVUNF error — design flattening in synthesis removes RTL hierarchy; replacing hierarchical references in testbench or preserving paths in synthesis (set_attribute preserve). Issue 3: FLFFNF error — compiled SDF file not found; using xmsdfc to compile SDF; the SDF_FILE keyword. Issue 4: SDFNEP and SDFNET warnings — path/check does not exist in HDL; SDF annotation translation rules for edge specifiers, IOPATH/TIMINGCHECK matching, and SETUPHOLD splitting with +sdf_splitvlog_suh.
Debug
Flow
VLSI Link
GLS-07
Issue 5: Debugging timing failures — reading the $setuphold violation message (instance path, time, file/line), design problem vs annotation problem, using SimVision waveforms to confirm SDF delay annotation, -sdf_verbose and -sdfstats for annotation debug. Issue 6: Glitch suppression cancellation — -ntc_verbose, monitors on NTC delayed signals, -nontcglitch switch. Issue 7: Pulse error warnings — +pulse_r/+pulse_e percentages, -epulse_no_msg to suppress. Issue 8: SDF delays not appearing — SDFNET/SDFNEP warnings, pulse rejection, $sdf_annotate log file, timescale/precision mismatch (rounding to zero), -override_precision, -dumptiming. Full NTC warning reference table: SDFNL2, SDFIND, NONTCTL, NTCTLER, NGLIM2, NTCWID, NTCNNC, NTCDNG, NTCRLX, NTCELX, NTCPAT, SDFNCAP, SDFNSB.
Debug
Hardware
VLSI Link
📌 GLS Quick Reference — Key Switches
DELAY MODE
-nospecify
+delay_mode_zero
+delay_mode_unit
+delay_mode_path
-maxdelays / -mindelays
SDF ANNOTATION
-sdf_cmd_file <file>
-sdf_file <arg>
-sdf_verbose
-sdfstats <file>
-sdf_simtime
TIMING CHECKS
-notimingchecks
-nonotifier
-no_tchk_msg
-ntcnotchks
-tfile <file>
PULSE CONTROL
-pulse_e <%>
-pulse_r <%>
-pulse_int_e <%>
-pulse_int_r <%>
-epulse_no_msg
DEBUG / RACE
-gateloopwarn
-races
-seq_udp_delay
-sequdp_nba_delay
-dumptiming <file>
NTC / PRECISION
-ntcnotchks
-ntc_tolerance
-ntc_neglim
-override_precision
-timescale <t/p>
Series structure: 7 articles across 3 units. Unit 1 (GLS-01, GLS-02) establishes why GLS exists and how the three simulation modes and two delay models work. Unit 2 (GLS-03, GLS-04, GLS-05) covers SDF back-annotation, timing check control, and first-time flow setup with a real counter example. Unit 3 (GLS-06, GLS-07) is a practical debug guide for all common GLS issues — from zero-delay gate loops to NTC convergence failures — with exact error mnemonics, causes, and resolutions.