Series Wrap-Up — Digital Electronics — VLSI Trainers Digital Electronics Series · Complete You Made It 🎉 12 articles, 6 units, 85+ worked examples, and a clear line from flip-flops all the way to DRAM cells and the memory hierarchy. Here’s a look back at everything you picked up. 🗺️ The journey, unit by unit […]
Digital Electronics Series -Wrap_up Read More »
Welcome to the Digital Electronics Series — VLSI Trainers VLSI Trainers · Digital Electronics Series Welcome to the Digital Electronics Series 👋 What this series covers, who it’s for, how each article is structured, and what you’ll be able to do when you’re done — read this before starting. 💡 Why this series exists Digital
Welcome to the Digital Electronics Series Read More »
Digital Electronics Series — Complete Index — VLSI Trainers VLSI Trainers · Digital Electronics Series Complete Digital Electronics Series Index Every article in the series, in order. Click any card to go directly to that article. 12Articles 6Units 85+Worked Examples 0Prerequisites Beyond Basics Start Here Welcome to the Digital Electronics Series 👋 What this series
Complete Digital Electronics Series Index Read More »
DE-12: Digital Memories — VLSI Trainers Digital Electronics Series · DE-12 Digital Memories Memory parameters (MAR, MBR, access time, volatility) — ROM, PROM, EPROM, EEPROM — SRAM and DRAM cell structures — RAM ICs (7489, 2147, 4164) — ROM applications — Magnetic disk, floppy, hard disk, bubble memory, CCD, CD-ROM — and the VLSI memory
Learn PCIe Configuration Space Type 1 Header used by bridges and root ports. Understand primary, secondary and subordinate bus numbers, I/O and memory base/limit registers, and bridge control fields in PCIe Gen6.
PCIe Bridge Configuration Space — Type 1 Header Guide Read More »
Learn PCIe Configuration Space Type 0 Header in detail. Understand Vendor ID, Device ID, Command and Status registers, Class Code, BARs, Subsystem fields, and Capability Pointer used in PCIe endpoint enumeration.
PCIe Configuration Space Type 0 Header Explained Read More »
Learn PCIe Link Training and LTSSM including all 11 LTSSM states and substates. Understand Detect, Polling, Configuration, Recovery, and L0 state transitions in PCIe Gen6.
PCIe LTSSM Explained — Link Training and All 11 States Read More »
PCIe Series — PCIe-16: 128b/130b Encoding (Gen 3+) — VLSI Trainers PCIe Series · PCIe-16 128b/130b Encoding (Gen 3+) Why 8b/10b was abandoned at Gen 3, how 128b/130b works — 16-byte data blocks, the 2-bit sync header, block types, framing tokens, the Gen 3 scrambler, block alignment, and how the encoding carries through Gen 4,
PCIe 128b/130b Encoding Explained — Gen3 and Beyond Read More »
PCIe Series — PCIe-15: 8b/10b Encoding — VLSI Trainers PCIe Series · PCIe-15 8b/10b Encoding Why raw binary can’t be sent directly on a PCIe link — the three problems 8b/10b solves, how a 5b/6b + 3b/4b split works, Current Running Disparity, special control characters (K-codes), the 20% overhead and why it matters, and what
PCIe 8b/10b Encoding Explained — Working, Disparity and Overhead Read More »
PCIe Series — PCIe-14: Physical Layer — Lanes, Differential Signalling & Electrical — VLSI Trainers PCIe Series · PCIe-14 Physical Layer — Lanes, Differential Signalling & Electrical What a PCIe lane actually is at the wire level — one differential pair in each direction, AC coupling, differential and common-mode voltage, characteristic impedance, why differential signalling
PCIe Physical Layer Explained — Lanes, Differential Signalling and Electricals Read More »
