VLSI Trainers · SystemVerilog Series
Complete SystemVerilog Series Index
Every post in the series, in order. Click any card to go directly to that article.
42Total Posts
4Phases
27Core SV Topics
0Prerequisites Beyond Basics
Start Here
Welcome to the SystemVerilog Series 👋
What this series is, who it’s for, what you’ll learn, and how we approach every post — read this first.
Series Complete
You Made It — A Look Back at Everything 🎉
A casual recap of every major skill and concept you picked up across all 27 SV posts.
Phase 1
Language Foundation
SV-01
›
Introduction
What SV adds over Verilog-2001 and the design philosophy behind it
SV-02
›
Literal Values
Integer, real, string, time literals; X, Z, and based number notation
SV-03
›
Data Types
bit, logic, byte, int, real, shortreal, string, chandle, void — and when to use each
SV-04a
›
Packed & Unpacked Arrays
Dimensions, slices, memory layout differences, and multi-dimensional indexing
SV-04b
›
Dynamic Arrays
new(), delete(), runtime sizing, and common dynamic array patterns
SV-04c
›
Associative Arrays, Queues & Array Methods
Key-value maps, FIFO queues, sort, find, unique, and all built-in array manipulation methods
SV-05a
›
Data Declarations & Constants
parameter, localparam, const, typedef, enum, struct, union declarations
SV-05b
›
Variables, Scope, Nets & Type Compatibility
Lifetime, visibility, net types, implicit conversions, and type-checking rules
SV-06
›
Attributes
The (* *) syntax and how tools use attributes for synthesis and lint hints
SV-07a
›
Operators & Expressions
Arithmetic, logical, bitwise, relational, shift, conditional, and reduction operators
SV-07b
›
Real Operators, Size, Sign, Precedence & Built-in Methods
Expression sizing rules, signed/unsigned, operator precedence, and string/integer methods
SV-07c
›
Concatenation, Array, Struct & Tagged Union Expressions
Static prefixes, replication, aggregate expressions, and tagged union access
SV-07d
›
Aggregate Expressions, Operator Overloading, Streaming & inside
Streaming operators {<<}, {>>}, the inside operator, and overloaded operators in classes
Phase 2
Hardware Modelling
SV-08a
›
Procedural Statements & Control Flow
if-else, unique if, priority if, case, unique case, casex, casez
SV-08b
›
Loops, Jump Statements, Final Blocks & Labels
for, while, do-while, foreach, repeat, break, continue, return, final blocks
SV-08c
›
Disable, Event Control, Level-Sensitive Sequences & Procedural Assign
disable, @, wait, wait fork, and the deprecated procedural assign/deassign
SV-09a
›
Processes — always_comb, always_ff, always_latch & Continuous Assignments
When to use which always variant, implicit sensitivity lists, and assign statements
SV-09b
›
fork…join, Process Threads & Fine-Grain Process Control
join, join_any, join_none, disable fork, wait fork, and process handles
SV-10
›
Tasks, Functions & Argument Passing
Automatic vs static, input/output/inout/ref directions, default values, prototype declarations
SV-14
›
Scheduling Semantics
The stratified event scheduler — eleven time-slot regions, the iterative loop, and PLI callbacks
Phase 3
Verification
SV-11a
›
Classes, Objects & Methods
Full OOP model — inheritance, virtual, polymorphism, casting, handles, constructors
SV-12
›
Random Constraints
rand, randc, constraint blocks, solve-before, dist, inside, weighted randomisation
SV-13
›
Interprocess Synchronization
Semaphores, mailboxes, typed mailboxes, events, wait_order, event merging and null
SV-15
›
Clocking Blocks
Input/output skew, #1step, ## cycle delay, default clocking, synchronous drives
SV-16
›
Program Block
Reactive region scheduling, race elimination, $exit, blocking tasks from programs
SV-17a
›
Assertions — Immediate & Concurrent Overview
Immediate assertions, severity levels, sampled values, the triggered property, boolean expressions
SV-17b
›
Sequences
## concatenation, [*] [->] [=] repetition, throughout, within, binsof, local variables, subroutines on match
SV-17c
›
Properties, Multi-Clock, Concurrent Assertions & Binding
|-> and |=>, disable iff, recursive properties, multi-clock, assert/assume/cover, bind
SV-20
›
Coverage — covergroup, Points & Classes
Covergroup as a type, coverage points, cross, clocking events, formal arguments, embedded in classes
SV-20b
›
Coverage Points, Cross, Options & Methods
Bins, transitions, wildcard, ignore/illegal bins, binsof, instance/type options, coverage methods
Phase 4
Integration & The Language Ecosystem
SV-18
›
Hierarchy — Packages, $unit, $root & Modules
Packages, import/::, compilation-unit scope, nested modules, extern modules, timeunit/timeprecision
SV-18b
›
Ports, Module Instances, Port Rules & Name Spaces
.name, .* connections, port direction inheritance, variable port rules, eight name spaces
SV-19
›
Interfaces
Modports, clocking blocks, tasks/functions, export/import, extern forkjoin, virtual interfaces
SV-21
›
Parameters
Typed value parameters, type parameters, $isunbounded, $ token, parameterised checkers
SV-22
›
Configuration Libraries
Libraries, cells, config declarations, and the one SV extension to the cell set
SV-23
›
System Tasks & System Functions
$typeof, $bits, array query functions, assertion control tasks, $readmem/$writemem, multi-dim arrays
SV-24
›
VCD Data
How SV types map into standard VCD waveform dumps — packed arrays, structs, enums
SV-25
›
Compiler Directives
‘define enhancements — `” `\`” “ tokens, macro-based ‘include, angle-bracket ‘include form
SV-26
›
Deprecated Features
Why defparam and procedural assign/deassign are deprecated — the problems and the alternatives
SV-27
›
Direct Programming Interface (DPI)
import/export, pure/context qualifiers, open arrays, WYSIWYG principle, disable protocol