Functional Verification in VLSI — Complete Guide
Learn functional verification in VLSI — simulation, synthesis, testbenches, and how RTL designs are verified before silicon tapeout.
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Verilog_Course
Verilog HDL — Complete Series
Learn Verilog HDL from beginner to advanced with a structured 18-part series covering syntax, RTL, FSMs, simulation, and verification.
VERILOG DESIGNS · MODULE 39
Verilog Designs — 64-bit Pipelined Multiplier — VLSI Trainers Verilog Designs · Module 39 64-bit Pipelined Multiplier Four implementations of a 64-bit pipelined integer multiplier — naive partial-product tree, carry-save adder (CSA) reduction, Wallace tree with 4-stage pipeline, and a signed/unsigned configurable variant — with detailed partial-product generation, CSA reduction diagrams, throughput analysis, and an
Verilog Designs · Modules 36 & 37
Verilog Designs — Synchronous & Asynchronous FIFO — VLSI Trainers Verilog Designs · Modules 36 & 37 Synchronous & Asynchronous FIFO Complete FIFO implementations — synchronous FIFO with counter-based flags, synchronous FIFO with pointer comparison, asynchronous FIFO with Gray-coded pointers and 2-FF synchronisers, and a parameterised async FIFO — with full/empty flag derivation, waveforms, and
Verilog Designs · Module 35
Verilog Designs — Dual Port RAM 128×8 — VLSI Trainers Verilog Designs · Module 35 Dual Port RAM — 128×8 Complete dual-port RAM designs — True Dual Port (TDP) with independent read/write on both ports, Simple Dual Port (SDP) with dedicated write and read ports, dual-clock SDP for clock domain crossing, and a FIFO-ready dual-port
Compiler Directives, Hierarchical Access & UDPs in Verilog
Learn Verilog compiler directives, hierarchical access, and User-Defined Primitives (UDPs) with combinational and sequential examples.
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Verilog Compiler Directives Explained
Learn Verilog parameters, specify blocks, path delays, and compiler directives like `define, `include, and `timescale with examples.
System Tasks, Functions & File I/O in Verilog — Complete Guide
Learn Verilog system tasks, functions, and file I/O — display, simulation control, math, random, conversions, and file handling with examples.
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Switch Level — Delays, Strengths & Tri-reg
Learn Verilog switch-level delays, drive strengths, strength resolution, and trireg capacitive nets with practical modeling examples.
Switch Level Modelling in Verilog — Complete Guide
Learn switch-level Verilog modeling using NMOS, PMOS, CMOS, and bidirectional switch primitives with transistor-level examples.
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