// ── Sized numbers ─────────────────────────────────────────────
4'b1010        // 4-bit  binary   → decimal 10
8'hFF          // 8-bit  hex      → decimal 255
6'd35          // 6-bit  decimal  → binary 100011
12'o777        // 12-bit octal    → binary 111_111_111

// ── X and Z values in binary ──────────────────────────────────
4'b1x0z        // bit 3=1, bit 2=unknown, bit 1=0, bit 0=high-Z
8'bxxxx_zzzz   // upper nibble unknown, lower nibble high-Z
4'bx           // all 4 bits unknown  (x extends to fill width)
4'bz           // all 4 bits high-Z   (z extends to fill width)

// ── Signed numbers ────────────────────────────────────────────
4'sb1011       // signed 4-bit: = -5 in 2's complement
8'sd-20        // signed 8-bit decimal -20

// ── Underscore for readability (ignored by compiler) ──────────
16'b1010_0101_1100_0011   // groups of 4 bits
32'h_DEAD_BEEF             // hex groups of 4

// ── Unsized (avoid in RTL — 32-bit default) ───────────────────
255            // 32-bit decimal 255
'b1010        // unsized binary — width inferred from context

// String in $display — most common use
$display("Simulation started at time %0t", $time);
$display("Result = %0d (expected 255)", result);

// Storing a string in a reg
// "numb" = 4 chars × 8 bits = 32 bits needed
reg [31:0] str_reg;
str_reg = "numb";
// Stored as: n=8'h6E, u=8'h75, m=8'h6D, b=8'h62
// str_reg = 32'h6E_75_6D_62

// String in file I/O
integer fh;
fh = $fopen("output.txt", "w");
$fwrite(fh, "Test PASS\n");
$fclose(fh);

// Escape sequences inside strings
"\n"   // newline
"\t"   // tab
"\\"   // backslash
"\""   // double quote
"%d %b %h %o"  // format specifiers for $display

// ── Value 0 and 1: normal driven states ──────────────────────
assign y = 1'b0;             // y = 0
assign y = 1'b1;             // y = 1

// ── Value x: unknown / uninitialized ─────────────────────────
reg q;                       // q starts as x at simulation start
wire w = a & b;              // if a or b is x, w is x
4'bx                         // all 4 bits = x (extends to fill)

// ── Value z: high-impedance (tri-state) ───────────────────────
assign bus = oe ? data : 8'bz; // float bus when oe=0
wire undriven;               // unconnected wire → z by default

// supply0 always wins over weak1
supply0 gnd;              // strength 7, value 0
wire    net;

assign (weak1, weak0) net = 1'b1;  // strength 4, value 1
assign gnd;             // strength 7, value 0 — wins
// Result: net = 0  (supply beats weak)

// Equal strength conflict → x
assign (strong1, strong0) net = 1'b1;   // strong 1
assign (strong1, strong0) net = 1'b0;   // strong 0
// Result: net = x  (equal strengths conflict)

// wire: driven by assign or module port ─────────────────────
wire y;
assign y = a & b;          // ✅ wire driven by assign

wire sum;
adder u1 (.sum(sum), ...);  // ✅ wire driven by module output

// reg: driven by always or initial block ─────────────────────
reg q;
always @(posedge clk)
  q <= d;                   // ✅ reg driven by always → flip-flop

reg combo;
always @(*)
  combo = a | b;            // ✅ reg driven by always → combinational

// ❌ Common mistakes ─────────────────────────────────────────
wire bad;
always @(*) bad = x;       // ❌ cannot drive wire from always

reg bad2;
assign bad2 = x;           // ❌ cannot use assign on reg (illegal)

// ── Scalar (1-bit, no range) ──────────────────────────────────
wire       wr;          // 1-bit net
reg        flag;        // 1-bit register

// ── Vectors (multi-bit) ───────────────────────────────────────
wire [7:0]  data;        // 8-bit bus  — data[7]=MSB, data[0]=LSB
reg  [3:0]  nibble;      // 4-bit reg
reg  [31:0] word;         // 32-bit reg

// ── Signed vectors ────────────────────────────────────────────
wire signed [7:0] s_data; // signed: range -128 to +127
reg  signed [3:0] s_reg;  // signed: range -8 to +7

// ── Bit-select (access a single bit) ─────────────────────────
data[0]                    // LSB of data
data[7]                    // MSB of data

// ── Part-select (slice a range of bits) ──────────────────────
data[7:4]                  // upper nibble
data[3:0]                  // lower nibble

// ── Indexed part-select (Verilog-2001) ────────────────────────
data[4 +: 4]               // bits [7:4] — start at 4, width 4, going up
data[7 -: 4]               // bits [7:4] — start at 7, width 4, going down

// parameter — overridable at instantiation time
parameter  DATA_W  = 8;
parameter  DEPTH   = 16;

// localparam — internal constant, cannot be overridden from outside
localparam ADDR_W  = $clog2(DEPTH);   // derived from DEPTH
localparam MAX_VAL = ((1 << DATA_W) - 1);

// Multiple parameters in one declaration
parameter MEM_SIZE = 256,
           WORD_W  = 32,
           FACTOR  = WORD_W / 2;

// defparam (legacy — avoid in new code)
adder_n u3 (...);
defparam u3.N = 64;    // override N — works but discouraged