LEARN · BUILD · VERIFY
AMBA 3 APB
on EDA Playground
A 5-phase, 3-month learning series. Build a spec-compliant APB implementation from scratch, verify every timing diagram, and sign off with a clean 13-test regression — all in your browser.
Reference spec:
ARM IHI 0024B — AMBA 3 APB Protocol Specification v1.0
5 phases · 13 weeks · zero install required
Each post = one playground. Paste design.sv + testbench.sv → Run → done.
01
Spec & Environment Setup
Parameter package, the 10 APB signals (Table 4-1), SystemVerilog interface with modports, and 6 always-on SVA protocol assertions.
›
02
RTL Implementation
APB master with IDLE→SETUP→ACCESS FSM. APB slave with 8×32-bit register file, PREADY wait-state extension, and PSLVERR error response.
›
03
Functional Verification
7 directed tests — one per spec timing diagram. Write/read with and without wait states, failing write and read with PSLVERR, back-to-back transfers.
›
04
Integration & Interface Testing
System-level tests: PSLVERR→BRESP[1] AXI mapping, PSLVERR→HRESP[0] AHB mapping (§2.3.3), reset sequence, and synchronous-transition checks.
›
05
Sign-off Regression
All 13 tests in one simulation. Zero failures required to tag v1.0. Full EPWave trace covers every test group. Share this playground as your APB implementation proof.
›
Before you start
What you need
A browser and an EDA Playground account (free, Google/GitHub login). No software installation required.
Recommended simulator
Aldec Riviera-PRO for full SystemVerilog + SVA support. Icarus Verilog 12 works for Phases 1–5 but won’t fire SVA.
Background assumed
Basic SystemVerilog (always_ff, typedef, enum). No APB knowledge required — the spec is explained at every step.
