PCIe Series — PCIe-12: Data Link Layer — DLLPs and Reliability — VLSI Trainers PCIe Series · PCIe-12 Data Link Layer — DLLPs and Reliability How the Data Link Layer guarantees reliable TLP delivery — DLLP types and formats, sequence numbers, LCRC, the Replay Buffer, the ACK/NAK protocol, REPLAY_TIMER, and how Gen 6 flit-based reliability […]
PCIe DLLPs Explained: ACK/NAK, Replay and Sequence Numbers Read More »
PCIe Series — PCIe-11: Address Translation — AT Field, ATS, and PRI — VLSI Trainers PCIe Series · PCIe-11 Address Translation — AT Field, ATS, and PRI The 2-bit Address Type field in every TLP header, why IOMMUs need hardware address translation support, how Address Translation Services negotiate translated addresses, and how the Page Request
Learn DAC and ADC in digital electronics — weighted resistor and R-2R DACs, Flash, SAR, Counter-ramp and Dual-slope ADCs, DAC0808, ADC0801, performance metrics, and mixed-signal VLSI design concepts.
Learn counters in digital electronics — asynchronous ripple counters, synchronous binary counters, up/down counters, Mod-N design, decade counters, counter ICs (7490, 74163, 74190), and VLSI applications.
Learn shift registers in digital electronics — SISO, SIPO, PISO, PIPO, bidirectional and universal shift registers, ring and Johnson counters, ICs 7491/74164/74194/74195, and practical applications.
Learn flip-flops in digital electronics — RS latch, D flip-flop, JK flip-flop, T flip-flop, race-around condition, Master-Slave JK, asynchronous preset/clear, excitation tables, and flip-flop conversion with examples.
Learn logic families in digital electronics — RTL, DTL, TTL, Schottky TTL, ECL, NMOS, PMOS, and CMOS with fan-in, fan-out, propagation delay, noise margin, power dissipation, and comparison tables.
Understanding RTL, DTL, TTL, ECL and CMOS Logic Families Read More »
PCIe Series — PCIe-10: TLP Ordering Rules — VLSI Trainers PCIe Series · PCIe-10 TLP Ordering Rules Why order matters in a packet-switched fabric, the three TLP categories, the complete ordering table explained in plain English, the Producer/Consumer model that motivates it all, deadlock prevention, Relaxed Ordering, ID-Based Ordering, and Gen 6. Contents Why Ordering
PCIe Series — PCIe-09: Message TLPs — VLSI Trainers PCIe Series · PCIe-09 Message TLPs Msg and MsgD — why messages exist, the 4DW header in full detail, all six routing codes, INTx interrupt signalling, power management messages, error messages, slot power limit, vendor-defined messages, LTR, OBFF, and how all of this carries forward unchanged
PCIe Message TLPs Explained — Msg and MsgD in Detail Read More »
PCIe Series — PCIe-08: Configuration TLPs — VLSI Trainers PCIe Series · PCIe-08 Configuration TLPs CfgRd0, CfgRd1, CfgWr0, CfgWr1 — how the 3DW configuration header works, what Type 0 vs Type 1 means, how Bus/Device/Function addressing targets config space, Type 1 to Type 0 conversion at switches, Extended Register Number, and how all of this
PCIe Configuration TLPs Explained — CfgRd0, CfgRd1, CfgWr0 and CfgWr1 Read More »
