UVM_Course

UVM-12: Sequences — VLSI Trainers VLSI VLSI Trainers UVM Series · UVM-12 UVM Series · UVM-12 Sequences The sequence as a transient object — body() task, the start_item/finish_item handshake, how sequences start on a sequencer, rand fields in sequences, sub-sequences, the API sequence pattern, linear and parallel execution, and sequence hierarchy from atomic to test-level. […]

UVM-11: Sequence Items — VLSI Trainers VLSI VLSI Trainers UVM Series · UVM-11 UVM Series · UVM-11 Sequence Items Designing the foundation of all UVM stimulus — the four field categories, rand vs non-rand convention, the `uvm_field automation macros, implementing do_copy / do_compare / do_print / convert2string manually, constraints, and the complete APB sequence item

UVM-10: Factory Overrides in Practice — VLSI Trainers VLSI VLSI Trainers UVM Series · UVM-10 UVM Series · UVM-10 Factory Overrides in Practice Practical patterns for using the UVM factory — type overrides vs instance overrides, when to apply each, the abstract/concrete component pattern for protocol-agnostic environments, sequence overrides, and command-line override plusargs. Contents Quick

UVM-09: Configuration Objects — VLSI Trainers VLSI VLSI Trainers UVM Series · UVM-09 UVM Series · UVM-09 Configuration Objects Designing configuration objects that mirror the testbench hierarchy, nested configs, the configure_* virtual function pattern for extensible base tests, configuring sequences through the sequencer, and the params package for compile-time constants. Contents Why Config Objects Anatomy

UVM-08: uvm_config_db — VLSI Trainers VLSI VLSI Trainers UVM Series · UVM-08 UVM Series · UVM-08 uvm_config_db The complete config_db API — set() and get() signatures, the four-part key, path wildcards and precedence, what types can be stored, the exists() and dump() debug methods, and every common pitfall explained with the exact fix. Contents What

UVM-07: Virtual Interfaces — VLSI Trainers VLSI VLSI Trainers UVM Series · UVM-07 UVM Series · UVM-07 Virtual Interfaces The two-kingdom problem — why class-based testbenches cannot directly access DUT signals, what a virtual interface is, the recommended config_db pattern for passing virtual interfaces, clocking blocks, and the most common pitfalls. Contents The Two-Kingdom Problem

UVM-06: Block-Level Testbench — VLSI Trainers VLSI VLSI Trainers UVM Series · UVM-06 UVM Series · UVM-06 Block-Level Testbench A complete step-by-step walkthrough of building a block-level UVM testbench from scratch — SV top module, sequence item, driver, monitor, agent config, agent, environment config, environment, base test, and the sequence that drives it all. Contents

UVM-05: The UVM Agent — VLSI Trainers VLSI VLSI Trainers UVM Series · UVM-05 UVM Series · UVM-05 The UVM Agent The agent as a reusable verification kit for one protocol interface — active vs passive modes, the is_active flag, the agent configuration object pattern, how sequencer, driver, and monitor are built and connected inside

UVM-04: The UVM Factory — VLSI Trainers VLSI VLSI Trainers UVM Series · UVM-04 UVM Series · UVM-04 The UVM Factory How the UVM factory works, why create() must always be used instead of new(), the registration macros for components and objects, type overrides and instance overrides, how polymorphism makes overrides work, and the complete

UVM-03: UVM Phases — VLSI Trainers VLSI VLSI Trainers UVM Series · UVM-03 UVM Series · UVM-03 UVM Phases The complete UVM phase system — all 12 standard phases, execution order and direction, function phases vs task phases, the run-time sub-phases, phase objections, drain time, phase_ready_to_end, and common phase mistakes that break simulations. Contents Phase