Verilog Compiler Directives Explained
Learn Verilog parameters, specify blocks, path delays, and compiler directives like `define, `include, and `timescale with examples.
May 2026
System Tasks, Functions & File I/O in Verilog — Complete Guide
Learn Verilog system tasks, functions, and file I/O — display, simulation control, math, random, conversions, and file handling with examples.
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Switch Level — Delays, Strengths & Tri-reg
Learn Verilog switch-level delays, drive strengths, strength resolution, and trireg capacitive nets with practical modeling examples.
Switch Level Modelling in Verilog — Complete Guide
Learn switch-level Verilog modeling using NMOS, PMOS, CMOS, and bidirectional switch primitives with transistor-level examples.
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Numbers, Strings, Logic, Data Types & Operators in Verilog
Learn Verilog numbers, strings, logic values, data types, vectors, parameters, and every operator category with clear examples.
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Behavioral Modelling in Verilog — Part 4
Learn advanced Verilog behavioral modeling — while and forever loops, fork-join parallel blocks, force-release, and events with RTL examples.
Behavioral Modelling in Verilog — Part 3
Learn advanced Verilog behavioral modeling — if/else, assign-deassign, repeat, for loops, disable statements, and synthesizable examples.
Behavioral Modelling in Verilog — Part 2
Learn advanced behavioral modeling in Verilog — delayed assignments, wait, multiple always blocks, blocking vs non-blocking, case statements, and simulation flow.
Behavioral Modelling in Verilog — Complete Guide
Learn behavioral modeling in Verilog — procedural constructs, blocking vs non-blocking assignments, and initial/always blocks with examples.
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Modelling at Data Flow Level — Complete Verilog Guide
Learn Verilog data-flow modeling — continuous assignments, signal driving, delays, vector assignments, and operators with practical examples.
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