Learn 8-bit population count (popcount) in Verilog using combinational, serial, parallel, and tree-adder implementations with testbenches.
Count the Number of 1s — Popcount Circuit in Verilog Read More »
Learn overlapping 1101 sequence detector design in Verilog using Mealy and Moore FSMs with RTL, state diagrams, and testbench.
Overlapping 1101 Sequence Detector Using Mealy and Moore Machines Read More »
Learn 1101 sequence detector FSM design in Verilog using Mealy and Moore machines with state diagrams, RTL code, and testbench.
Sequence Detector 1101 Using Mealy and Moore Machines Read More »
Learn D flip-flop design in Verilog with synchronous and asynchronous reset, timing diagrams, characteristic tables, and testbenches.
D Flip-Flop — Synchronous & Asynchronous Reset in Verilog Read More »
Verilog Designs — ALU with Testbench — VLSI Trainers Verilog Designs · Module 23 8-bit ALU — Design & Testbench Complete 8-bit Arithmetic Logic Unit with 8 operations — addition, subtraction, AND, OR, XOR, NOT, shift-left, shift-right — zero, carry, negative and overflow flags, plus an exhaustive self-checking testbench covering all operation codes. 📋 Contents
Learn 2-to-1 and 4-to-1 multiplexer design in Verilog using case statements, logic equations, and ternary operators with testbenches.
Multiplexer — Three Implementation Styles in Verilog Read More »
Learn a 4-bit ripple carry adder in Verilog built from gates → half adder → full adder with exhaustive testbench and waveforms.
4-bit Full Adder using Half Adder — Design & Testbench Read More »
Learn 1-bit full adder design in Verilog at gate, dataflow, behavioral, and structural levels with a self-checking testbench.
1-bit Full Adder — Design & Testbench in Verilog Read More »
Learn half adder design in Verilog at gate, dataflow, behavioral, and UDP levels with self-checking testbench, waveforms, and logs.
Learn Verilog compiler directives, hierarchical access, and User-Defined Primitives (UDPs) with combinational and sequential examples.
Compiler Directives, Hierarchical Access & UDPs in Verilog Read More »
