System Tasks, Functions & File I/O

// ── Basic $display ────────────────────────────────────────────
$display("Hello Verilog!");              // prints with newline
$display("a = %b, b = %d", a, b);        // formatted output

// ── $write — no automatic newline ─────────────────────────────
$write("Part1 ");
$write("Part2 ");
$display("Part3");   // output: "Part1 Part2 Part3\n"

// ── $strobe — always shows final stable values ────────────────
always @(posedge clk) begin
  q <= d;
  $display("$display: q=%b", q);   // may show OLD q (pre-NBA)
  $strobe ("$strobe:  q=%b", q);   // always shows NEW q ✅
end

// ── $monitor — fires automatically on any signal change ───────
initial $monitor("t=%0t a=%b b=%b out=%b", $time, a, b, out);
// Prints every time a, b, or out changes — no explicit call needed

// ── Suppress monitor during initialization ────────────────────
initial begin
  $monitoroff;         // pause — suppress noise during reset
  rst_n = 0; #20;
  rst_n = 1; #5;
  $monitoron;          // resume — start logging from here
end

reg [7:0] data = 8'hAB;
integer    cnt  = 42;

// All numeric formats for the same value
$display("Binary  : %b",  data); // Binary  : 10101011
$display("Octal   : %o",  data); // Octal   : 253
$display("Decimal : %d",  data); // Decimal :         171 (width-padded)
$display("Decimal : %0d", data); // Decimal : 171     (no padding)
$display("Hex     : %h",  data); // Hex     : ab
$display("Hex UC  : %H",  data); // Hex UC  : AB

// Time and module path
$display("Time=%0t  Module=%m", $time); // Time=100  Module=tb.u_dut

// Multi-signal formatted line
$display("[%0t] data=0x%h cnt=%0d", $time, data, cnt);
// [100] data=0xab cnt=42

// $timeformat: sets how %t appears globally
// $timeformat(units, precision, suffix, min_width);
$timeformat(-9, 2, " ns", 10); // -9=ns, 2 decimal places
$display("Time = %t", $time);    // Time =  100.00 ns

integer pass_count=0, fail_count=0;

task check_result;
  input [7:0] expected, actual;
  input [63:0] test_id;
  begin
    if (actual === expected) begin
      $display("PASS [%0d] expected=%h got=%h", test_id, expected, actual);
      pass_count = pass_count + 1;
    end else begin
      $error("FAIL [%0d] expected=%h got=%h", test_id, expected, actual);
      fail_count = fail_count + 1;
    end
  end
endtask

initial begin
  // ... run all tests ...
  #1000;

  // Final summary
  $display("\n===== RESULTS: %0d PASS / %0d FAIL =====",
           pass_count, fail_count);

  if (fail_count > 0)
    $fatal(1, "%0d test(s) failed", fail_count); // non-zero exit
  else
    $finish;   // success — exit normally
end

`timescale 1ns/1ps

// ── Reading current time ──────────────────────────────────────
initial begin
  #10.5;
  $display("$time     = %0t",    $time);     // 10  (rounded to 1ns)
  $display("$realtime = %0.3f",   $realtime); // 10.500 (ps precision)
end

// ── $timeformat configuration ─────────────────────────────────
// $timeformat(time_unit, decimal_places, suffix, min_field_width)
$timeformat(-9, 3, " ns", 12);
// -9 = nanoseconds, 3 decimal places, suffix " ns", min width 12

$display("Current time = %t", $time);   // "   10.000 ns"

// ── Measuring interval between events ────────────────────────
integer t_start, t_end;
initial begin
  t_start = $time;
  @(posedge done);
  t_end   = $time;
  $display("Operation took %0d ns", t_end - t_start);
end

// ── $clog2 — synthesizable, used in parameter expressions ─────
parameter DEPTH  = 256;
localparam ADDR_W = $clog2(DEPTH);     // = 8
localparam CNT_W  = $clog2(DEPTH+1);   // = 9 (count 0..256)
reg [ADDR_W-1:0] ptr;                    // [7:0] — auto-sized

// ── Real math in testbench ────────────────────────────────────
real freq_hz, period_ns, amplitude;
freq_hz   = 1e9;                           // 1 GHz
period_ns = 1e9 / freq_hz;               // 1.0 ns

// Sine wave stimulus generation
real pi = 3.14159265;
integer i;
initial
  for (i=0; i<360; i=i+1) begin
    amplitude = $sin(i * pi / 180.0);
    $display("%0d deg: sin = %.4f", i, amplitude);
  end

// ── $rtoi / $itor ─────────────────────────────────────────────
real    r  = 3.75;
integer n  = $rtoi(r);       // n = 3 (truncated)
real    r2 = $itor(n * 2);   // r2 = 6.0

// ── $realtobits / $bitstoreal — transfer reals across ports ───
module top;
  real   r_val = 3.14;
  wire [63:0] wire_bits;
  real   r_recv;

  assign wire_bits = $realtobits(r_val);  // pack real as 64-bit
  assign r_recv    = $bitstoreal(wire_bits); // unpack on other side
endmodule

// ── $signed / $unsigned — arithmetic interpretation ───────────
reg [7:0] a = 8'hFF;       // bit pattern: 11111111

$display("unsigned: %0d", a);               // 255
$display("signed:   %0d", $signed(a));     // -1

// Signed arithmetic comparison
if ($signed(a) < 0)
  $display("a is negative when treated as signed");

// ── $random: basic usage ─────────────────────────────────────
reg [7:0] rand_byte;
rand_byte = $random;         // lower 8 bits of 32-bit random
rand_byte = $random % 256;  // same — forces 0..255

// ── Bounded random — common patterns ─────────────────────────
integer r;
r = {$random} % 16;        // {} makes it unsigned → 0..15
r = ($random % 10) + 1;   // 1..10

// ── With seed for reproducible sequences ─────────────────────
integer seed = 42;
r = $random(seed);          // seed is modified each call

// ── Generate random test packet ───────────────────────────────
reg [7:0] pkt [0:63];
integer pkt_len, i;
pkt_len = ({$random} % 60) + 4;  // 4..63 bytes
for (i=0; i<pkt_len; i=i+1)
  pkt[i] = $random;

// ── $dist_uniform — clean bounded generation (PLI) ───────────
integer seed2 = 1234;
r = $dist_uniform(seed2, 0, 255);   // uniform 0..255

initial begin
  // ── Configure waveform dump ───────────────────────────────
  $dumpfile("sim_output.vcd");    // VCD output file name
  $dumpvars(0, tb);               // dump ALL signals in tb hierarchy
  $dumpvars(1, tb.dut);           // dump only top-level of dut
  $dumpvars(0, tb.dut.alu);       // dump all of alu sub-module

  // Apply reset stimulus...
  $dumpoff;                        // stop recording during reset
  rst_n = 0; #20; rst_n = 1;
  $dumpon;                         // resume recording

  // Run tests...
  #5000;
  $finish;
end

// ── Memory load tasks (often used with waveform) ──────────────
reg [7:0] rom [0:255];
initial begin
  $readmemh("program.hex", rom);         // load hex file into array
  $readmemh("data.hex", rom, 10, 20);   // load into addresses 10..20
  $readmemb("data.bin", rom);            // load binary format
  $writememh("out.hex", rom);           // write memory to file
end

integer log_fd, ref_fd;

initial begin
  // ── Open files ────────────────────────────────────────────
  log_fd = $fopen("sim_log.txt",  "w");   // write new log
  ref_fd = $fopen("reference.hex", "r");  // read reference

  // ── Always check for open failure (fd=0 means failure) ───
  if (log_fd == 0) begin
    $display("ERROR: Cannot open sim_log.txt");
    $finish;
  end

  // ── Use files... ──────────────────────────────────────────
  $fdisplay(log_fd, "Simulation started at t=%0t", $time);

  // ── Always close before $finish ───────────────────────────
  $fclose(log_fd);
  $fclose(ref_fd);
  $finish;
end

// ── Multi-channel write — OR descriptors together ─────────────
integer f1, f2, both;
f1   = $fopen("file1.txt", "w");
f2   = $fopen("file2.txt", "w");
both = f1 | f2;          // write to BOTH at once
$fdisplay(both, "This goes to both files!");

integer fd;
reg [7:0] data;

initial begin
  fd = $fopen("output.csv", "w");

  // Write CSV header
  $fdisplay(fd, "time_ns,data_hex,data_dec,data_bin");

  // Write data rows as simulation runs
  repeat(16) begin
    @(posedge clk);
    $fdisplay(fd, "%0t,%h,%0d,%b", $time, data, data, data);
  end

  // Write without newlines then add one manually
  $fwrite(fd, "Summary: ");
  $fwrite(fd, "16 samples written");
  $fwrite(fd, "\n");          // manual newline

  // Write to console AND file simultaneously
  $fdisplay(fd | 1, "Done!"); // fd|1: fd=file, 1=stdout

  $fclose(fd);
end

// ── $fscanf: read test vectors from CSV ───────────────────────
integer    fd, n;
reg [7:0] in_a, in_b, expected;
string     line;

initial begin
  fd = $fopen("vectors.txt", "r");
  if (fd == 0) begin $fatal(1, "Cannot open vectors.txt"); end

  // File format example (one test per line):
  //   0xAB 0xCD 0x01
  //   0xFF 0x00 0xFF

  while (!$feof(fd)) begin
    n = $fscanf(fd, "%h %h %h\n", in_a, in_b, expected);
    if (n == 3) begin            // 3 items matched
      @(posedge clk);
      a = in_a; b = in_b;
      @(posedge clk);
      if (result !== expected)
        $error("FAIL: a=%h b=%h exp=%h got=%h", in_a, in_b, expected, result);
    end
  end
  $fclose(fd);
end

// ── $sscanf: parse a string in memory ────────────────────────
reg [255:0] str_buf;
integer     val1, val2;

str_buf = "0xAB 0xCD";
n = $sscanf(str_buf, "%h %h", val1, val2);
// n=2, val1=8'hAB, val2=8'hCD

// ── $fgetc: read character by character ──────────────────────
integer fd, ch;
fd = $fopen("input.txt", "r");

while (1) begin
  ch = $fgetc(fd);
  if (ch == -1) break;          // -1 = EOF
  if (ch == "\n") $display(""); // newline
  else            $write("%c", ch);
end
$fclose(fd);

// ── $fgets: read a whole line ─────────────────────────────────
reg [1023:0] line_buf;    // wide enough for 128 chars
integer fd2, ret;
fd2 = $fopen("log.txt", "r");

while (!$feof(fd2)) begin
  ret = $fgets(line_buf, fd2);  // ret=0 success, -1=EOF
  if (ret != -1)
    $display("Line: %s", line_buf);
end
$fclose(fd2);

module golden_tb;
  reg  [7:0] a, b;
  wire [7:0] result;
  reg        clk = 0;

  alu_dut dut(.a(a), .b(b), .out(result));
  always #5 clk = ~clk;

  integer stim_fd, gold_fd, log_fd;
  integer n, pass=0, fail=0;
  reg [7:0] exp;

  initial begin
    stim_fd = $fopen("stimulus.txt", "r");
    gold_fd = $fopen("golden.txt",   "r");
    log_fd  = $fopen("results.log",  "w");

    $fdisplay(log_fd, "%-8s %-8s %-8s %-8s %-5s",
              "time", "a", "b", "result", "PASS?");

    while (!$feof(stim_fd)) begin
      n = $fscanf(stim_fd, "%h %h\n", a, b);   // read a, b
      n = $fscanf(gold_fd, "%h\n",    exp);     // read expected
      @(posedge clk); #1;

      if (result === exp) begin
        $fdisplay(log_fd, "%t %h %h %h PASS", $time, a, b, result);
        pass++;
      end else begin
        $fdisplay(log_fd, "%t %h %h %h FAIL(exp=%h)",
                  $time, a, b, result, exp);
        fail++;
      end
    end

    $fdisplay(log_fd, "\nTotal: %0d pass, %0d fail", pass, fail);
    $fclose(stim_fd); $fclose(gold_fd); $fclose(log_fd);
    if (fail) $fatal(1, "%0d failures", fail);
    else      $finish;
  end
endmodule

integer log_fd;

initial begin
  // VCD waveform
  $dumpfile("waves.vcd");
  $dumpvars(0, tb);

  // Text log
  log_fd = $fopen("sim.log", "w");
  $timeformat(-9, 2, " ns", 10);

  // fd|1 writes to both log file AND console (fd=1 is stdout)
  $fmonitor(log_fd | 1,
    "%t clk=%b d=%b q=%b", $time, clk, d, q);

  #200;
  $fclose(log_fd);
  $finish;
end