Modelling at Data Flow Level

// y = ~((a & b) | (c & d))

// ── Gate Level (structural) ────────────────────────────────────
wire ab, cd;
and  g1 (ab, a, b);
and  g2 (cd, c, d);
nor  g3 (y,  ab, cd);

// ── Data Flow Level (continuous assignment) ────────────────────
assign y = ~((a & b) | (c & d));   // ✅ one line, no intermediate wires

// ── Behavioural Level (procedural) ────────────────────────────
always @(*) y = ~((a & b) | (c & d));

// ── Form 1: Explicit assign statement ─────────────────────────
wire y;
assign y = a & b;             // declared separately, then assigned

// ── Form 2: Inline assign during net declaration ───────────────
wire y = a & b;               // declare and assign in one line

// ── Form 3: Drive strength specified ──────────────────────────
assign (strong1, weak0) y = a & b;  // explicit drive strengths

// ── Form 4: Multiple targets (separate statements) ─────────────
assign sum  = a ^ b;
assign cout = a & b;            // both run simultaneously always

// ── All four styles below are equivalent ──────────────────────
assign y1 = ~a;
assign y2 = ~a;
assign y3 = ~a;              // three drivers on three different nets — legal

// Basic gates
assign y_and  = a & b;
assign y_or   = a | b;
assign y_xor  = a ^ b;
assign y_not  = ~a;
assign y_nand = ~(a & b);
assign y_nor  = ~(a | b);

// 2-to-1 Multiplexer
assign mux_out = sel ? a : b;

// 4-to-1 Multiplexer (nested ternary)
assign mux4 = (sel==2'b00) ? in0 :
              (sel==2'b01) ? in1 :
              (sel==2'b10) ? in2 : in3;

// Half adder
assign sum  = a ^ b;
assign cout = a & b;

// Full adder
assign {cout, sum} = a + b + cin;

// Priority encoder (4-to-2)
assign code = in[3] ? 2'b11 :
              in[2] ? 2'b10 :
              in[1] ? 2'b01 : 2'b00;

// Tri-state driver
assign bus = oe ? data : 8'bz;

// Comparator
assign eq  = (a == b);
assign gt  = (a >  b);
assign lt  = (a <  b);

// ── Single delay — same for all transitions ────────────────────
assign #10       y = a & b;    // 10 time units for any 0→1 or 1→0

// ── Two delays — (rise_delay, fall_delay) ─────────────────────
assign #(3, 5)   y = a & b;    // rise=3 time units, fall=5 time units

// ── Three delays — (rise, fall, turn-off to z) ─────────────────
assign #(2, 4, 1) bus = oe ? data : 8'bz; // rise=2, fall=4, z=1

// ── Min:Typ:Max — process variation corners ────────────────────
assign #(1:2:4)   y = a | b;    // min=1, typical=2, max=4

// ── With timescale ────────────────────────────────────────────
`timescale 1ns/100ps
assign #2.5      y = a ^ b;    // 2.5 ns propagation delay

// ── Full vector assignment ─────────────────────────────────────
wire [7:0] a, b, y;
assign y = a & b;          // 8-bit bitwise AND — all bits simultaneously
assign y = a + b;          // 8-bit addition
assign y = ~a;             // bitwise invert all 8 bits

// ── Bit-select (access one bit) ───────────────────────────────
wire       msb, lsb;
assign msb = a[7];          // drive scalar from one bit of vector
assign lsb = a[0];

// ── Part-select (slice of bits) ───────────────────────────────
wire [3:0] upper, lower;
assign upper = a[7:4];       // upper nibble of a
assign lower = a[3:0];       // lower nibble of a

// ── Concatenation on LHS ──────────────────────────────────────
wire [8:0] result;
assign {cout, result[7:0]} = a + b;   // split 9-bit sum

// ── Concatenation on RHS ──────────────────────────────────────
wire [15:0] word;
assign word = {a, b};        // join two 8-bit signals into 16-bit word

// ── Replication ───────────────────────────────────────────────
wire [31:0] sign_ext;
assign sign_ext = {{24{a[7]}}, a};  // sign-extend 8-bit to 32-bit

// ── Indexed part-select (Verilog-2001) ────────────────────────
wire [7:0] byte_n;
assign byte_n = word[8*1 +: 8];   // byte 1 of word (bits [15:8])

wire [31:0] data32;
wire [1:0]  byte_sel;    // selects which byte: 0,1,2,3
wire [7:0]  byte_out;

// ✅ Variable base with constant width — works in Verilog-2001+
assign byte_out = data32[8*byte_sel +: 8];
// byte_sel=0 → data32[7:0]
// byte_sel=1 → data32[15:8]
// byte_sel=2 → data32[23:16]
// byte_sel=3 → data32[31:24]

// ❌ Variable in constant part-select — NOT allowed
// assign byte_out = data32[8*byte_sel+7 : 8*byte_sel];  // illegal

module alu_8bit (
  input  [7:0] a, b,
  input  [2:0] op,          // operation select
  output [7:0] result,
  output       zero,        // result is zero
  output       carry
);
  wire [8:0] add_result;

  // Intermediate — full adder with carry
  assign add_result = a + b;

  // Select operation using nested ternary (priority mux)
  assign result =
    (op == 3'b000) ? add_result[7:0] :   // ADD
    (op == 3'b001) ? (a - b)        :   // SUB
    (op == 3'b010) ? (a & b)        :   // AND
    (op == 3'b011) ? (a | b)        :   // OR
    (op == 3'b100) ? (a ^ b)        :   // XOR
    (op == 3'b101) ? ~a             :   // NOT a
    (op == 3'b110) ? (a << 1)       :   // SHL
                      (a >> 1);           // SHR (default)

  // Status flags using reduction and relational operators
  assign zero  = ~|result;              // reduction NOR — 1 if result=0
  assign carry = add_result[8];          // carry-out from adder
endmodule