📋 What Verilog-2001 Provided

Verilog-2001 provided two compiler directives relevant here:

• ‘define — text-substitution macro with optional arguments. Arguments replace named tokens in the macro body verbatim. A backslash at end-of-line continues the macro body onto the next line.
• ‘include — file inclusion directive. Accepts only a double-quoted literal filename: 'include "filename".

// Verilog-2001 'define with arguments — unchanged in SV
`define NAND(dval) nand #(dval)
`NAND(3)       i1 (y, a, b);    // expands to: nand #(3) i1 (y, a, b)
`NAND(3:4:5)   i2 (o, c, d);    // expands to: nand #(3:4:5) i2 (o, c, d)

SV adds three new escape sequences inside macro bodies and extends 'include with an angle-bracket form. All existing Verilog-2001 macro behaviour is unchanged.

📋 New ‘define Escape Tokens

SV adds three special tokens that can appear inside a macro body, enabling two new capabilities — building string literals from macro arguments and concatenating tokens to form identifiers.

📋 Backtick-Quote — Building String Literals from Arguments

Placing `" at the beginning and end of a section of the macro body makes the argument values appear inside a string literal in the expansion. Without `", a macro argument is substituted as raw tokens — not wrapped in quotes.

// Verilog-2001 style
`define show(x) $display(x)
`show(hello)
// expands to: $display(hello)
// ERROR: hello is an identifier, not a string

// SV style — `" wraps the argument
`define show(x) $display(`"x`")
`show(hello)
// expands to: $display("hello")
// OK: hello is now a string literal

📋 Backtick-Backslash-Backtick-Quote — Embedded Escaped Quotes

To include a literal escaped quote (\") inside a string being built by the macro, use the sequence `\`". This lets you construct strings with embedded double-quote characters.

// Build a string that includes inner quoted text
// Macro: `define msg(x,y) `"x: `\`"y`\`"`"
`define msg(x,y) `"x: `\`"y`\`"`"

// Call:
$display(`msg(left side, right side));

// Expands to:
$display("left side: \"right side\"");

// Output when executed:
// left side: "right side"

📋 Double-Backtick — Token Concatenation

Two adjacent backticks (``) in a macro body act as a token-boundary marker without introducing any whitespace. This lets you build a single identifier by concatenating a macro argument with fixed text.

// Build a signal name by appending a suffix to the argument
`define foo(f) f``_suffix

`foo(bar)
// expands to: bar_suffix  (one identifier, no space)

// Without ``:
`define foo2(f) f_suffix
`foo2(bar)
// expands to: bar _suffix  (TWO tokens with whitespace — probably wrong)

// Practical use: generate unique instance names
`define MAKE_FF(name) ff_d name``_inst (.d(name``_d), .q(name``_q), .clk(clk));
`MAKE_FF(data)
// expands to: ff_d data_inst (.d(data_d), .q(data_q), .clk(clk));

📋 Including a File via a Macro

The 'include directive can now be followed by a macro expansion instead of a literal string, as long as the macro expands to a double-quoted filename.

// Define a macro that expands to a quoted path
`define home(filename) `"/home/foo/filename`"

// Use the macro with 'include
`include `home(myfile)
// expands 'include to:  'include "/home/foo/myfile"

📋 ‘include with Angle Brackets

SV adds a second form of the 'include directive using angle brackets, modelled after the C language #include <file> convention. It searches only the vendor-defined location where standard library files are installed, rather than the user’s project file paths.

// Double-quote form (Verilog-2001, unchanged):
// Searches project include paths (tool-specific order)
`include "my_header.svh"

// Angle-bracket form (new in SV):
// Searches only the vendor-defined standard location
`include <sv_standard_lib.svh>

// Relative paths inside <> are relative to the vendor location, not the project
`include <ieee/uvm_pkg.svh>

📋 Quick Reference