Verilog Designs — 64-bit Pipelined Multiplier — VLSI Trainers Verilog Designs · Module 39 64-bit Pipelined Multiplier Four implementations of a 64-bit pipelined integer multiplier — naive partial-product tree, carry-save adder (CSA) reduction, Wallace tree with 4-stage pipeline, and a signed/unsigned configurable variant — with detailed partial-product generation, CSA reduction diagrams, throughput analysis, and an […]
Verilog Designs — Synchronous & Asynchronous FIFO — VLSI Trainers Verilog Designs · Modules 36 & 37 Synchronous & Asynchronous FIFO Complete FIFO implementations — synchronous FIFO with counter-based flags, synchronous FIFO with pointer comparison, asynchronous FIFO with Gray-coded pointers and 2-FF synchronisers, and a parameterised async FIFO — with full/empty flag derivation, waveforms, and
Verilog Designs — Dual Port RAM 128×8 — VLSI Trainers Verilog Designs · Module 35 Dual Port RAM — 128×8 Complete dual-port RAM designs — True Dual Port (TDP) with independent read/write on both ports, Simple Dual Port (SDP) with dedicated write and read ports, dual-clock SDP for clock domain crossing, and a FIFO-ready dual-port
Learn 128×8 single-port RAM design in Verilog with sync/async read, read-first/write-first modes, byte enable, and testbenches.
Single Port RAM (128×8) — Design & Testbench in Verilog Read More »
Learn 4-bit LFSR design in Verilog with Fibonacci, Galois, PRBS generators, tap polynomials, and exhaustive testbenches.
Learn N-bit universal shift register design in Verilog with hold, shift, load, arithmetic, rotate modes, and exhaustive testbenches.
N-bit Universal Shift Register in Verilog — Complete Guide Read More »
Learn PIPO shift register design in Verilog with clock enable, bidirectional and universal modes, waveforms, and testbenches.
Parallel-In Parallel-Out Shift Register Design in Verilog Read More »
Learn synchronous up-down counter design in Verilog with load, Gray-code variant, waveforms, and exhaustive testbenches.
Learn clock divider design in Verilog — divide-by-2, even/odd divide-by-N, fractional dividers, waveforms, and verification testbenches.
Learn Binary-to-Gray and Gray-to-Binary conversion in Verilog with XOR logic, parameterized design, truth tables, and exhaustive testbenches.
Binary to Gray Code Conversion in Verilog — Complete Guide Read More »
