// ============================================================
// Testbench  : pipe_mult_tb
// DUTs       : pipe_mult_tree, pipe_mult_csa,
//              pipe_mult_wallace, pipe_mult_signed
// Strategy   : Drive inputs every cycle, collect outputs
//              valid_out latency=4. Compare with $unsigned
//              or $signed reference from Verilog operator.
// Test cases :
//   1. Boundary: 0*0, 0*MAX, MAX*MAX, 1*X
//   2. Powers of 2: 2^k * 2^m for all k,m in 0..63
//   3. Random: 200 random 64-bit pairs
//   4. Signed: -1*1, -1*-1, MIN*MIN, MIN*-1
//   5. Back-to-back pipeline: verify no bubble between results
// ============================================================
`timescale 1ns/1ps
`default_nettype none

module pipe_mult_tb;
  reg clk=0, rst_n=1, valid_in=0, signed_op=0;
  reg [63:0] a=0, b=0;
  wire [127:0] p_tree, p_csa, p_wall, p_sign;
  wire vo_tree, vo_csa, vo_wall, vo_sign;

  pipe_mult_tree    u_t(.clk(clk),.rst_n(rst_n),.valid_in(valid_in),
                        .a(a),.b(b),.product(p_tree),.valid_out(vo_tree));
  pipe_mult_csa     u_c(.clk(clk),.rst_n(rst_n),.valid_in(valid_in),
                        .a(a),.b(b),.product(p_csa),.valid_out(vo_csa));
  pipe_mult_wallace u_w(.clk(clk),.rst_n(rst_n),.valid_in(valid_in),
                        .a(a),.b(b),.product(p_wall),.valid_out(vo_wall));
  pipe_mult_signed  u_s(.clk(clk),.rst_n(rst_n),.valid_in(valid_in),
                        .signed_op(signed_op),
                        .a(a),.b(b),.product(p_sign),.valid_out(vo_sign));

  always #5 clk=~clk;
  initial begin $dumpfile("pipe_mult.vcd"); $dumpvars(0,pipe_mult_tb); end

  // Reference queue: store expected values in order of valid_in pulses
  reg [127:0] exp_q[0:255];
  integer wr_idx=0, rd_idx=0;
  integer pass_cnt=0, fail_cnt=0, test_num=0;

  task drive;
    input [63:0] ta,tb; input [127:0] exp;
    begin
      a=ta; b=tb; valid_in=1;
      exp_q[wr_idx % 256] = exp; wr_idx++;
      @(posedge clk); #1; valid_in=0;
    end
  endtask

  // Collect results when valid_out
  always @(posedge clk) begin
    if(vo_tree) begin
      test_num++;
      if(p_tree===exp_q[rd_idx%256] && p_wall===exp_q[rd_idx%256]) begin
        pass_cnt++;
        $display("  PASS [%3d] product=%h",test_num,p_tree);
      end else begin
        fail_cnt++;
        $display("  FAIL [%3d] tree=%h wall=%h exp=%h",
          test_num,p_tree,p_wall,exp_q[rd_idx%256]);
      end
      rd_idx++;
    end
  end

  integer k;
  reg [63:0] ra,rb;

  initial begin
    $display("\n======================================================");
    $display("  64-bit Pipelined Multiplier Testbench");
    $display("======================================================");
    rst_n=0; repeat(2) @(posedge clk); #1; rst_n=1;

    // Boundary cases
    $display("\n  --- Boundary cases ---");
    drive(64'h0,   64'h0,   128'h0);
    drive(64'hFFFF_FFFF_FFFF_FFFF, 64'h0, 128'h0);
    drive(64'h1,   64'hFFFF_FFFF_FFFF_FFFF,
          128'h0000_0000_0000_0000_FFFF_FFFF_FFFF_FFFF);
    drive(64'hFFFF_FFFF_FFFF_FFFF,
          64'hFFFF_FFFF_FFFF_FFFF,
          128'hFFFF_FFFF_FFFF_FFFE_0000_0000_0000_0001);

    // Powers of two: 2^k * 2^m = 2^(k+m)
    $display("\n  --- Powers of two ---");
    for(k=0;k<64;k=k+8)
      drive(64'h1<<k, 64'h1<<k, 128'h1<<(2*k));

    // Random tests
    $display("\n  --- Random 64-bit pairs (200 tests) ---");
    for(k=0;k<200;k=k+1) begin
      ra = {$random,$random};
      rb = {$random,$random};
      drive(ra, rb, ra * rb);
    end

    // Wait for all outputs
    repeat(8) @(posedge clk); #1;

    $display("\n======================================================");
    $display("  RESULTS: %0d / %0d PASS  |  %0d FAIL",pass_cnt,test_num,fail_cnt);
    $display("======================================================");
    if(fail_cnt==0) $display("  ALL TESTS PASSED\n");
    else $fatal(1,"  %0d FAILURE(S)\n",fail_cnt);
    #20; $finish;
  end
endmodule
`default_nettype wire