PCIe Series — PCIe-10: TLP Ordering Rules — VLSI Trainers PCIe Series · PCIe-10 TLP Ordering Rules Why order matters in a packet-switched fabric, the three TLP categories, the complete ordering table explained in plain English, the Producer/Consumer model that motivates it all, deadlock prevention, Relaxed Ordering, ID-Based Ordering, and Gen 6. Contents Why Ordering […]
PCIe Series — PCIe-09: Message TLPs — VLSI Trainers PCIe Series · PCIe-09 Message TLPs Msg and MsgD — why messages exist, the 4DW header in full detail, all six routing codes, INTx interrupt signalling, power management messages, error messages, slot power limit, vendor-defined messages, LTR, OBFF, and how all of this carries forward unchanged
PCIe Message TLPs Explained — Msg and MsgD in Detail Read More »
PCIe Series — PCIe-08: Configuration TLPs — VLSI Trainers PCIe Series · PCIe-08 Configuration TLPs CfgRd0, CfgRd1, CfgWr0, CfgWr1 — how the 3DW configuration header works, what Type 0 vs Type 1 means, how Bus/Device/Function addressing targets config space, Type 1 to Type 0 conversion at switches, Extended Register Number, and how all of this
PCIe Configuration TLPs Explained — CfgRd0, CfgRd1, CfgWr0 and CfgWr1 Read More »
PCIe Series — PCIe-07: Completion TLPs — VLSI Trainers PCIe Series · PCIe-07 Completion TLPs The full Cpl and CplD header — Completer ID, Status codes, Byte Count, Lower Address, Requester ID, and Tag — plus split-completion mechanics, Completion Timeout, CplLk/CplDLk for locked transactions, and what none of this changes in Gen 6. Contents What
PCIe Series — PCIe-06: Memory Read and Write TLPs — VLSI Trainers PCIe Series · PCIe-06 Memory Read and Write TLPs Full bit-level headers for MRd, MWr, and MRdLk — 3DW and 4DW variants side by side, Requester ID, Tag, Byte Enables explained with worked examples, address rules, the 4 KB boundary constraint, and how
PCIe Series — PCIe-05: TLP Structure — Common Header Fields — VLSI Trainers PCIe Series · PCIe-05 TLP Structure — Common Header Fields Every TLP starts with the same first Doubleword. This post dissects it bit by bit — Fmt, Type, TC, LN, TH, TD, EP, Attr (RO, NS, IDO), AT, and Length — with
PCIe Series — PCIe-04: PCIe Generations Gen 1 to Gen 6 — VLSI Trainers PCIe Series · PCIe-04 PCIe Generations — Gen 1 to Gen 6 The bandwidth maths behind every generation, why each speed step chose its encoding scheme, what physical constraints drove each decision, and a deep dive into Gen 6’s PAM4 and
PCIe Series — PCIe-03: The Three-Layer Model in Detail — VLSI Trainers PCIe Series · PCIe-03 The Three-Layer Model in Detail How all three PCIe layers fit together — TLP header fields, flow control credits, virtual channels, the ACK/NAK state machine, the replay buffer, and how the Physical Layer changes completely from Gen 1 through
PCIe Series — PCIe-02: Architecture, Topology and Components — VLSI Trainers PCIe Series · PCIe-02 Architecture — Topology and Components Root Complex internals and how they appear to software, the Switch’s internal virtual bus structure, BDF addressing, how every port sees the same three layers, transaction types, and a complete step-by-step bus number enumeration walk-through.
PCIe Series — PCIe-01: Introduction to PCI Express — VLSI Trainers PCIe Series · PCIe-01 Introduction to PCI Express Why the parallel shared bus model hit a wall, how a serial point-to-point link sidesteps all three fundamental limits, the topology every PCIe system shares, the three-layer architecture, and how bandwidth has scaled from Gen 1’s
