TLP Structure — Common Header Fields

📋 What a TLP Is — Structure Overview

A Transaction Layer Packet (TLP) is how PCIe devices talk to each other. Every read request, write, completion, configuration access, interrupt signal, and error report travels as a TLP. The Transaction Layer builds TLPs on the transmit side and decodes them on the receive side. Everything below the Transaction Layer (Data Link Layer, Physical Layer) is plumbing — the TLP is the message.

📋 DW0 — Full Bit Map

DW0 is 32 bits. Each field lives at a fixed bit position. The receiver always parses bits 31 downto 0 in this exact layout. Reserved bits must be written as 0 and should be ignored on receipt.

📋 Fmt [30:28] — Format and Header Size

Fmt is a 3-bit field at DW0 bits 30:28. It tells the receiver two things simultaneously: how many DWs the header occupies (3 or 4) and whether a data payload follows the header. The receiver reads Fmt first — before anything else — to know how many bytes to collect for the header and whether to expect payload bytes after.

📋 Type [27:24] — TLP Type

Type is a 5-bit field at DW0 bits 27:24. Combined with Fmt it uniquely identifies the TLP. The receiver uses Type to select the correct parser for the remaining header DWs and to decide what action to take (route, consume, generate completion, etc.).

The full Type encoding table is covered in PCIe-06 through PCIe-09 as part of each specific TLP format. Below is a summary grouped by category:

📋 TC [22:20] — Traffic Class

TC is a 3-bit field at DW0 bits 22:20. It encodes a priority value from 0 (lowest, default) to 7 (highest). The TC travels unmodified with the TLP from requester to completer — it is never changed by a switch. Completions must carry the same TC value as the request that caused them.

At every switch port, the TC value is used to select which Virtual Channel (VC) buffer the TLP enters. TC 0 always maps to VC0. TC 1–7 can be mapped to VC0 or any implemented VC, configured via the TC/VC mapping register. TLPs of different TCs have no ordering relationship with each other — ordering rules only apply within the same TC.

📋 LN [18] — Lightweight Notification

LN is a 1-bit field at DW0 bit 18. It is also referred to as Attr[2] in some spec tables — though in the Gen 3 spec it was separated from the older Attr field to make room for IDO. When LN = 1, the TLP is tagged as a Lightweight Notification request — a mechanism that allows a downstream component to notify the Root Complex of specific events without generating a full Message TLP or interrupt.

LN is an optional feature. Most devices and most TLPs leave it at 0. LN = 1 requires both the sender and intermediate nodes to declare support for LN through configuration registers. For general-purpose PCIe design, treat LN = 0 as the normal state.

📋 TH [17] — TLP Processing Hints

TH is a 1-bit field at DW0 bit 17. When TH = 1, the TLP contains TLP Processing Hints (TPH) in the header — additional bytes that give the platform a hint about how to handle caching for this transaction. The TPH mechanism is aimed at optimising NUMA (Non-Uniform Memory Access) systems where a DMA device should write data to the memory controller closest to the CPU that will process it.

Like LN, TH = 1 is an optional feature that requires explicit hardware support. For IO and legacy TLP types the TH bit is always reserved (must be 0). For most general-purpose PCIe devices in a standard server or desktop, TH = 0.

📋 TD [16] — TLP Digest (ECRC Present)

TD is a 1-bit field at DW0 bit 16. When TD = 1, a 4-byte End-to-End CRC (ECRC) is appended to the end of the TLP — after the data payload, before the LCRC that the Data Link Layer adds. When TD = 0, no ECRC is present.

ECRC support is optional for endpoints but can be enabled via the AER Extended Capability registers. Both sender and receiver must agree to use ECRC. A device that does not support ECRC checking must still forward TLPs with TD=1 unchanged.

📋 EP [15] — Error Poisoned Data

EP is a 1-bit field at DW0 bit 15. When EP = 1, the payload data accompanying this TLP is marked as intentionally invalid. The TLP is allowed to complete normally — routing, flow control, and acknowledgement proceed as usual — but the final destination is told: “do not use this data, it is corrupt.”

When is EP set?

• Memory controller detects an ECC error in a read: the RC cannot return correct data, but it still returns a CplD. It sets EP=1 so the requester knows to treat the data as garbage.
• An MWr arrives with EP=1: the completer (memory controller, device register, etc.) must still accept the write’s flow-control credit and process it — but it should discard the data payload and report an error. It must not update the target register or memory with poisoned data.
• Propagation rule: if a device receives a read CplD with EP=1 and then uses that data in a subsequent write, it must set EP=1 in the write TLP too — propagating the poison flag forward so downstream devices know not to trust that data either.

📋 Attr [14:12] — Relaxed Ordering, No Snoop, IDO

Attr is a 3-bit field spanning DW0 bits 14 through 12. The three bits have independent meanings and are named separately in the spec:

All three Attr bits are forwarded unchanged through the fabric — a switch must not modify them. Completions must carry the same Attr values as the request that triggered them (with the exception that IDO may be set independently by the completer).

📋 AT [11:10] — Address Type

AT is a 2-bit field at DW0 bits 11:10. It supports Address Translation Services (ATS) and IOMMUs in virtualised systems. The field encodes whether the address in the TLP has been translated by an IOMMU or is still a “virtual” device address.

AT only applies to Memory and AtomicOp TLPs. For IO, Config, Message, and Completion TLPs, AT bits must be 00 (they are reserved or don’t apply). The AT field is covered in depth in PCIe-11 alongside ATS and the Page Request Interface (PRI).

📋 Length [9:0] — Payload Size in Doublewords

Length is a 10-bit field spanning DW0 bits 9:0 (Byte 2 bits 1:0, Byte 3 bits 7:0). It specifies the number of Doublewords (4-byte units) of data payload that follow the header. It applies only to TLPs that have a data payload (Fmt bit 29 = 1).

▶ Worked Example — Decoding a Real DW0

Let’s decode the hex value 0x40000010 — a typical DW0 from an MRd (Memory Read Request) for a 32-bit address.

⚡ DW0 in Gen 6 — What Changes

The answer is: nothing changes in DW0. Every field — Fmt, Type, TC, LN, TH, TD, EP, Attr (IDO, RO, NS), AT, Length — is identical in Gen 6 as in Gen 1. The TLP header format did not change across any PCIe generation.

In Gen 6, TLPs are physically packed into 256-byte flits by the Physical Layer before being sent over the link. From the Transaction Layer’s perspective, it builds exactly the same DW0 it always has and hands the complete TLP to the Data Link Layer. The Data Link Layer adds SeqNo and LCRC. The Physical Layer packs it into a flit. The receiver’s Physical Layer unpacks the flit and delivers the TLP upward — and the Transaction Layer decodes the same DW0 it has always decoded.

📋 Quick Reference — All DW0 Fields