Learn PCIe Base Address Registers (BARs) in detail. Understand memory vs I/O BARs, 32-bit and 64-bit BARs, prefetchable memory, BAR sizing algorithm, address allocation, and ROM BAR in PCIe Gen6.
PCIe BARs Explained — Base Address Registers in Detail Read More »
Learn PCIe Configuration Space Type 1 Header used by bridges and root ports. Understand primary, secondary and subordinate bus numbers, I/O and memory base/limit registers, and bridge control fields in PCIe Gen6.
PCIe Bridge Configuration Space — Type 1 Header Guide Read More »
Learn PCIe Configuration Space Type 0 Header in detail. Understand Vendor ID, Device ID, Command and Status registers, Class Code, BARs, Subsystem fields, and Capability Pointer used in PCIe endpoint enumeration.
PCIe Configuration Space Type 0 Header Explained Read More »
Learn PCIe Link Training and LTSSM including all 11 LTSSM states and substates. Understand Detect, Polling, Configuration, Recovery, and L0 state transitions in PCIe Gen6.
PCIe LTSSM Explained — Link Training and All 11 States Read More »
PCIe Series — PCIe-16: 128b/130b Encoding (Gen 3+) — VLSI Trainers PCIe Series · PCIe-16 128b/130b Encoding (Gen 3+) Why 8b/10b was abandoned at Gen 3, how 128b/130b works — 16-byte data blocks, the 2-bit sync header, block types, framing tokens, the Gen 3 scrambler, block alignment, and how the encoding carries through Gen 4,
PCIe 128b/130b Encoding Explained — Gen3 and Beyond Read More »
PCIe Series — PCIe-15: 8b/10b Encoding — VLSI Trainers PCIe Series · PCIe-15 8b/10b Encoding Why raw binary can’t be sent directly on a PCIe link — the three problems 8b/10b solves, how a 5b/6b + 3b/4b split works, Current Running Disparity, special control characters (K-codes), the 20% overhead and why it matters, and what
PCIe 8b/10b Encoding Explained — Working, Disparity and Overhead Read More »
PCIe Series — PCIe-14: Physical Layer — Lanes, Differential Signalling & Electrical — VLSI Trainers PCIe Series · PCIe-14 Physical Layer — Lanes, Differential Signalling & Electrical What a PCIe lane actually is at the wire level — one differential pair in each direction, AC coupling, differential and common-mode voltage, characteristic impedance, why differential signalling
PCIe Physical Layer Explained — Lanes, Differential Signalling and Electricals Read More »
PCIe Series — PCIe-13: Flow Control — VLSI Trainers PCIe Series · PCIe-13 Flow Control How PCIe prevents a fast transmitter from overwhelming a slow receiver — the six credit types (PH, PD, NPH, NPD, CPLH, CPLD), credit unit sizes, FC DLLP format, the two-phase FC_INIT handshake, infinite credits and why completions need them, UpdateFC
PCIe Flow Control Explained | Credits, Tags & Credit Return Read More »
PCIe Series — PCIe-12: Data Link Layer — DLLPs and Reliability — VLSI Trainers PCIe Series · PCIe-12 Data Link Layer — DLLPs and Reliability How the Data Link Layer guarantees reliable TLP delivery — DLLP types and formats, sequence numbers, LCRC, the Replay Buffer, the ACK/NAK protocol, REPLAY_TIMER, and how Gen 6 flit-based reliability
PCIe DLLPs Explained: ACK/NAK, Replay and Sequence Numbers Read More »
PCIe Series — PCIe-11: Address Translation — AT Field, ATS, and PRI — VLSI Trainers PCIe Series · PCIe-11 Address Translation — AT Field, ATS, and PRI The 2-bit Address Type field in every TLP header, why IOMMUs need hardware address translation support, how Address Translation Services negotiate translated addresses, and how the Page Request
