PCIe Generations — Gen 1 to Gen 6

📈 All Six Generations at a Glance

📋 How Bandwidth Is Calculated

The raw line rate (GT/s = Giga-Transfers per second) is the number of symbol transitions on the wire per second. That is not the same as data throughput — the encoding overhead must be subtracted.

📋 Gen 1 — 2.5 GT/s and 8b/10b

The first PCIe generation launched with the spec in 2003. The target was simple: be software-compatible with PCI while beating its bandwidth on a modern serial link.

Why 2.5 GT/s?

The 2.5 GHz bit clock was chosen as the highest frequency achievable with 2001-era CMOS process technology and standard PCB materials (FR4) at acceptable signal integrity margins. The transmitter spec required a differential swing of approximately 800 mV peak-to-peak, which is achievable without exotic processes.

Why 8b/10b?

8b/10b encoding was already proven in other serial protocols (Fibre Channel, SATA, USB 3.0). It delivers DC balance (essential for AC-coupled links), guaranteed transition density for CDR, and clear packet framing using K-characters. The 20% overhead was an acceptable cost in 2003 when the alternative was a parallel bus with 20× less bandwidth.

Special symbols (K-characters)

8b/10b reserves specific 10-bit patterns as control symbols with no 8-bit equivalent. PCIe uses these for framing and link management:

Gen 1 numbers

📋 Gen 2 — 5.0 GT/s, Same Encoding

Gen 2 (PCIe 2.0, 2007) doubled the line rate from 2.5 to 5.0 GT/s while keeping 8b/10b encoding. This was the simplest possible speed step — if the physical layer can clock twice as fast, you get twice the bandwidth. No encoding change required.

Why keep 8b/10b at 5 GT/s?

At 5 GT/s on FR4 PCB material, the channel loss is moderate but manageable with simple pre-emphasis at the transmitter. 8b/10b still works. The encoded symbols are wider in time (2 ns each) but the same framing and K-characters apply without modification. Changing the encoding would have broken backward compatibility with Gen 1 receivers.

What actually changed in Gen 2

• Higher frequency — pre-emphasis increased to compensate for greater channel loss at 5 GT/s
• Receiver equalization (CTLE — Continuous Time Linear Equalizer) added to boost high-frequency content at the input
• Tighter electrical specifications overall — jitter budgets tightened
• Otherwise identical to Gen 1 at the protocol level — same TLPs, same DLLPs, same framing

📋 Gen 3 — Why 8 GT/s, Not 10

This is the question everyone asks. If Gen 1 is 2.5 GT/s and Gen 2 is 5.0 GT/s — why is Gen 3 at 8 GT/s instead of 10 GT/s? The answer is in the encoding change.

128b/130b — what it buys

The transition from 8b/10b to 128b/130b in Gen 3 changes three things:

• Overhead drops from 20% to 1.54% — 128 data bits per 130-bit block instead of 8 per 10
• No more K-characters — framing moves to the sync header (2-bit prefix: 01=data block, 10=control block)
• Scrambling becomes mandatory and stronger — 128b/130b has no inherent DC balance, so a 23-bit LFSR scrambles all data to guarantee transition density for CDR lock

Gen 3 also added link equalisation

At 8 GT/s, the channel is lossy enough that simple pre-emphasis no longer suffices. Gen 3 introduced a formal link equalisation phase in the LTSSM — during link training, the two devices negotiate multi-tap FIR (Finite Impulse Response) filter coefficients. The transmitter and receiver exchange proposals and the best filter settings are selected before the link enters L0. This is entirely absent in Gen 1/2.

📋 Gen 4 — 16 GT/s, Pushing NRZ

Gen 4 (PCIe 4.0, 2017) doubled Gen 3’s line rate from 8 to 16 GT/s while keeping 128b/130b encoding. Same encoding change as Gen 2 was to Gen 1 — just crank the baud rate.

The Nyquist frequency jumps from 4 GHz to 8 GHz. This is still achievable on FR4 with aggressive equalization — multi-tap TX FIR coefficients, more powerful RX CTLE and DFE (Decision Feedback Equalizer). Channel trace lengths need to be shorter or use better PCB laminates.

• x1 throughput per direction: ~2 GB/s
• x16 aggregate: ~64 GB/s
• First generation where AI/ML workloads started driving the demand (GPU↔CPU at 32 GB/s bidirectional)
• First generation where PCIe retimers became common on server boards for longer traces

📋 Gen 5 — 32 GT/s, the NRZ Ceiling

Gen 5 (PCIe 5.0, 2019) doubled again to 32 GT/s, still using 128b/130b. Nyquist frequency is 16 GHz. At this speed, NRZ signalling on any realistic PCB trace length is at its practical limit.

Gen 5 pushed equalisation to its limits. Retimers (active repeaters) are effectively mandatory on server PCB designs for runs longer than 4–6 inches. Despite this, the protocol is unchanged — same 128b/130b, same TLPs and DLLPs, same software model.

• x1 throughput per direction: ~4 GB/s
• x16 aggregate: ~128 GB/s
• CXL 1.0/2.0 both run on PCIe 5.0 PHY
• First PCIe generation where retimers are practically mandatory in most designs

⚡ Gen 6 — 64 GT/s and Why Everything Changed

Gen 6 (PCIe 6.0, 2022) faces a hard constraint: NRZ signalling at 64 GT/s is physically impractical. Doubling to 64 GT/s with NRZ would mean a Nyquist frequency of 32 GHz — at that frequency, a 1-inch trace on FR4 has more than 20 dB of insertion loss. The signal would be unrecoverable without exotic and expensive channel materials.

The solution is a different modulation — PAM4 — combined with FEC and a new framing model. Gen 6 achieves 64 GT/s effective bit rate at only 32 GBaud (the same baud rate as Gen 5 at 32 GT/s NRZ), because PAM4 carries 2 bits per symbol.

📋 PAM4 Deep Dive — Symbols, Eyes, and BER

PAM4 (Pulse Amplitude Modulation with 4 levels) encodes 2 bits into each symbol by using four distinct voltage levels. The mapping is straightforward Gray-coded to minimise errors on adjacent levels:

📋 FEC Deep Dive — RS Codes and Correction Capability

Gen 6 uses a Reed-Solomon FEC code. The specific code parameters chosen by the PCIe 6.0 spec are RS(544, 514) — meaning 544 total symbols per codeword, 514 of which carry data and 30 carry parity. Each RS symbol is 10 bits wide.

📋 Flit Deep Dive — 256-byte Format and Protocol Impact

Gen 6 replaces start/end framing symbols with a flit-based framing model. A flit (flow control unit) is 256 bytes. Every flit is sent as a fixed-size container regardless of how many TLPs or DLLPs it carries.

📋 Clock Recovery Across Generations

Every PCIe generation embeds the clock in the data stream. There is no forwarded clock signal. The receiver uses a CDR (Clock and Data Recovery) circuit — typically a PLL — to lock onto the incoming bit transitions and extract the transmitter’s clock from them.

📋 Elastic Buffer — Handling ±300 ppm Clock Mismatch

Every PCIe receiver has an elastic buffer between the CDR and the Data Link Layer. Its purpose is to handle the small clock frequency difference between the transmitter and the receiver — even though both must be within ±300 ppm of the target frequency, the worst case is 600 ppm apart. That is 1 symbol difference every 1,666 symbols.

The elastic buffer absorbs this difference by adding or removing SKP symbols (Gen 1/2) or equivalent padding in Gen 3+ from the periodic SKIP ordered sets that arrive. Symbols are clocked into the buffer using the recovered clock (same rate as the transmitter) and clocked out using the local clock (which may be slightly faster or slower). Adding or removing a SKP symbol when the buffer level approaches overflow or underflow keeps the buffer within its safe operating range.

📋 Equalization — Gen 3 Through Gen 6

At Gen 1/2 speeds, a simple fixed pre-emphasis on the TX side is sufficient to compensate for PCB trace loss. From Gen 3 onwards, the channel loss is too severe and too variable for a fixed setting — an adaptive equalization process is built into the LTSSM link training sequence.

📋 Full Bandwidth Comparison — Every Width

📋 Quick Reference