Physical Layer — Lanes, Differential Signalling & Electrical

⚡ What a Lane Is

A PCIe lane is the fundamental unit of physical connectivity. Each lane consists of two differential pairs — one pair for transmitting data, one pair for receiving data. This makes PCIe full-duplex: both devices can transmit and receive simultaneously, without waiting for the other to finish.

Each differential pair carries one serial bitstream. There is no parallel bus — all bits for one lane travel down a single pair of conductors, one bit at a time, at the full link data rate. This is what “serial” means in PCI Express. The four conductors of a lane are the absolute minimum physical interface for one PCIe connection.

📋 Link Width — x1 through x16

A PCIe link can use multiple lanes in parallel to multiply bandwidth. The link width is expressed as x1, x2, x4, x8, x16, or x32. A x16 link has 16 TX pairs and 16 RX pairs — 64 conductors total. All lanes in a link operate at the same speed and carry independent bitstreams that are later reassembled into the original packet sequence.

Lane count negotiation happens during link training. A device advertises the number of lanes it supports; the two devices settle on the minimum of what both sides can use. The physical slot may have more lanes than the device uses — a x8 card in a x16 slot trains to x8. Unused lanes remain in electrical idle.

📋 Why Differential Signalling

At 2.5 GT/s (Gen 1) a bit time is 400 ps. At 64 GT/s (Gen 6) a bit time is 15.6 ps. Trying to transmit a reliable single-ended signal (one wire referenced to a shared ground) at 64 GT/s across a PCB trace would fail almost immediately — noise pick-up from adjacent signals, power supply ripple, and ground bounce would all corrupt the data.

Differential signalling solves this by using two wires instead of one. The transmitter drives D+ and D– to equal and opposite voltages. The receiver ignores the absolute voltage on either wire and instead only measures the difference between D+ and D–. Any noise that couples equally onto both conductors (common-mode noise) cancels out in the subtraction.

The benefits of differential signalling over single-ended at high speeds are:

• Common-mode noise rejection — any noise that couples equally onto both conductors vanishes in the subtraction. This includes power supply noise, crosstalk from adjacent signals, and EMI pick-up.
• Lower voltage swing requirement — the receiver responds to the difference between the two conductors, not the absolute voltage. PCIe can work with swings as small as 170 mV differential at the receiver in Gen 3 stressed conditions.
• No ground return needed — the two conductors reference each other. Ground potential variations between transmitter and receiver are common-mode and cancel out.
• Reduced EMI radiation — because D+ and D– carry equal and opposite signals, their radiation cancels in the far field, reducing electromagnetic interference emissions.

📋 Anatomy of a Differential Pair

A differential pair consists of two conductors — called D+ (or DP) and D– (or DN) — routed in close proximity from the transmitter to the receiver. For PCIe on a PCB, these are typically microstrip or stripline differential traces with controlled impedance. The physical characteristics of the pair are critical:

Within a pair, D+ and D– must be routed exactly the same length — even a few millimetres of length mismatch introduces intra-pair skew, meaning the two signals arrive at the receiver slightly offset in time. Intra-pair skew reduces the eye opening at the receiver. For Gen 5 and Gen 6, intra-pair skew targets are extremely tight — under 10 picoseconds in well-designed boards.

📋 Differential Voltage (VTX-DIFFp-p)

The transmitter drives D+ and D– to opposite polarities around the common-mode voltage. The peak-to-peak differential voltage (VTX-DIFFp-p) is the total swing from the most positive differential state to the most negative. This is the key electrical parameter that determines how much margin the signal has at the receiver after passing through the lossy PCB channel.

The transmitter voltage at the connector launch point (before the channel) is specified in the 800–1300 mV differential range. At the receiver, after the signal passes through PCB traces, connectors, and any internal package routing, the signal is attenuated and the eye may be much smaller. The receiver must be able to detect data down to its minimum sensitivity threshold.

📋 Common-Mode Voltage

The common-mode voltage (VCM) is the average voltage of D+ and D–: VCM = (V(D+) + V(D–)) / 2. When the transmitter drives a differential “1” (D+ high, D– low), both conductors have a DC bias component equal to VCM. The transmitter sets VCM to a specific level defined by the spec.

The receiver only responds to the difference V(D+) − V(D−). Common-mode variations (equal changes on both conductors) are rejected by the differential receiver’s CMRR (Common-Mode Rejection Ratio). However, very large common-mode voltages can push the input transistors outside their linear range — this is why the spec limits the common-mode AC ripple that a transmitter may inject.

📋 Impedance — Transmitter and Receiver

Characteristic impedance matching is essential at multi-gigabit data rates. Impedance mismatches create reflections — a portion of the signal bounces back toward the source, arriving at the receiver slightly delayed and adding noise to subsequent bits. This is one of the dominant sources of inter-symbol interference (ISI) at Gen 3 and above.

The transmitter has an internal termination resistor (ZTX) to match its output impedance to the channel. The receiver has an internal termination resistor (ZRX) to absorb the arriving signal without reflecting it back. Both are implemented as 50 Ω single-ended (100 Ω differential) resistors in the transmitter/receiver silicon, adjustable over a small range for calibration purposes.

📋 AC Coupling Capacitors

Every PCIe lane has AC coupling capacitors in series with each conductor of the differential pair. The spec requires at least one 75–265 nF capacitor per conductor, placed in the channel media (PCB) or inside the device package itself. The capacitor may be placed at either the transmitter end or the receiver end of the channel.

Why AC coupling is mandatory

• Prevents DC bias from transmitter from reaching the receiver. The transmitter’s internal DC bias (~0 V to ~3.3 V depending on the transistor technology) would saturate the receiver’s input transistors if directly connected. The capacitor blocks the DC component and passes only the high-frequency AC signal carrying data.
• Allows devices with different supply voltages to connect. A 3.3 V transmitter can connect to a 1.8 V receiver without voltage-level shifting circuits because the DC is blocked.
• Protects against electrostatic damage. Large voltage differentials that could occur during hot-plug events are blocked by the capacitor.

📋 Electrical Idle

When a transmitter wants to enter a low-power link state (L0s, L1, or L2), it transitions its output driver into electrical idle. In electrical idle the transmitter stops driving the differential pair — the output driver is tri-stated and the pair floats toward the common-mode voltage, with no AC signal present. The differential voltage falls below 20 mV peak.

The receiver detects electrical idle by monitoring for the absence of transitions. When the differential amplitude drops below the receiver’s electrical idle detect threshold (~100 mV for Gen 1/2), the receiver transitions its own state machine accordingly.

Entering and exiting electrical idle uses special Ordered Sets to signal intent to the far end — the Electrical Idle Ordered Set (EIOS) to enter, and the Electrical Idle Exit Ordered Set (EIEOS) to exit. This gives the receiver time to prepare its PLL and CDR circuits before data starts flowing again.

📋 De-emphasis and Pre-shoot

At high frequencies, PCB traces, vias, and connectors attenuate high-frequency content more than low-frequency content. This frequency-dependent loss means that long runs of consecutive identical bits (where the signal must hold a voltage level for many bit times) cause the signal to charge up further than it should — making the transition to the opposite polarity harder and creating Inter-Symbol Interference (ISI).

De-emphasis is a transmitter-side technique that deliberately reduces the voltage of bits that follow a bit of the same polarity. The first bit after a transition drives full amplitude. Subsequent bits of the same polarity are de-emphasised — reduced by 3.5 dB (Gen 1/2) or 6.0 dB (Gen 2 option, Gen 3+). This counteracts the channel’s tendency to overcharge for long constant-value runs.

Pre-shoot is the complement of de-emphasis — it applies to the last bit before a transition. Instead of reducing amplitude, it slightly boosts the pre-cursor bit to help the channel overcome the inertia of transitioning from one voltage to another. Together, de-emphasis and pre-shoot are the two coefficients of the transmitter’s 2-tap equalizer (de-emphasis only in Gen 1/2, extended to 3-tap FIR in Gen 3+).

📋 Equalization — Tx and Rx

As data rates increase, the PCB channel attenuates the signal more severely. Gen 1 links could get away with just de-emphasis. Gen 3 and above require full equalizer cooperation between transmitter and receiver. The equalization system is negotiated during link training in the Recovery state.

📋 Clock Tolerance and Spread Spectrum

The transmitter and receiver each run their own independent clocks. Even with a shared 100 MHz reference clock from the PCB, the internal PLLs can differ by up to ±300 ppm (600 ppm total). Over time this clock difference accumulates — the transmitter may be sending bits slightly faster or slower than the receiver’s clock expects.

PCIe handles this with two mechanisms:

• Elastic buffer — the receiver’s Data Link Layer has a first-in-first-out buffer that can absorb small clock differences by adding or removing entries. It runs off the recovered clock on one side and the local clock on the other.
• SKIP Ordered Sets — the transmitter periodically inserts SKIP characters (a specific K-character sequence) into the bitstream. The receiver can delete these characters if its elastic buffer is filling up (receiver clock faster than transmitter), or add extra SKIPs if the buffer is draining too fast (receiver clock slower). This is clock tolerance compensation — typically performed every 1538 symbol times in Gen 1/2.

Spread Spectrum Clocking (SSC) is an optional feature where the transmitter modulates its clock frequency by up to −0.5% (downspread only) at a low frequency (30–33 kHz). This spreads the EMI energy from the fundamental clock frequency across a range of frequencies, reducing peak emissions. The PCIe spec requires that if SSC is used it must be downspread only (never upspread), to prevent the clock from ever running faster than the nominal rate.

⚡ PAM4 — Gen 6 Electrical Signalling

Gen 1 through Gen 5 all use NRZ (Non-Return-to-Zero) signalling — each UI (Unit Interval, one bit time) carries exactly one bit. The differential signal is either positive (bit 1) or negative (bit 0). Doubling the data rate means halving the bit time, which halves the time available for the signal to reach a stable voltage — this rapidly becomes physically unachievable as bit times shrink below 30 ps.

Gen 6 breaks this barrier by switching to PAM4 (Pulse Amplitude Modulation, 4 levels). Instead of two signal levels (0, 1), PAM4 uses four levels. Each UI now encodes two bits simultaneously — doubling the data throughput at the same symbol rate as Gen 5.

PAM4 trade-offs vs NRZ

⚡ Gen 6 Electrical Parameters

Gen 6 introduces PAM4 signalling at 32 Gbaud (32 billion symbols per second) per lane. At this rate, the bit time is 31.25 ps (for each PAM4 symbol). The electrical challenges are extreme — the eye openings are small and equalization is complex. The Gen 6 electrical specification is defined in the PCIe 6.0 specification (released 2022) and includes:

• Symbol rate: 32 Gbaud per lane (64 Gbps effective data rate per lane)
• Modulation: PAM4 with Gray coding (00→01→11→10) to minimise bit errors when misdetecting an adjacent level
• FEC: Reed-Solomon RS(544,514) is mandatory — operates on 256-byte flits, corrects up to 15 symbol errors per flit
• Equalization: Tx 3-tap FIR mandatory, Rx CTLE + multi-tap DFE, adaptive equalization training required during link training
• Low-loss channel required: At 16 GHz Nyquist frequency (for 32 Gbaud), standard FR4 has 8–12 dB/inch loss. Gen 6 requires low-loss Megtron-class laminates and careful connector selection
• Reach: Gen 6 channel reach is specification-dependent — typically 8–12 inches on a high-quality server motherboard, considerably shorter than Gen 3 on standard FR4
• AC coupling: Still required — same capacitor range as Gen 3–5
• Differential impedance: Still 85–100 Ω — unchanged from previous generations

📋 Quick Reference