8b/10b Encoding

📋 Why Raw Binary Cannot Be Sent

It seems logical to just send raw binary data directly onto the PCIe differential pair — if the byte is 0xFF (all ones), drive D+ high for eight consecutive bit times. But this creates three serious problems for the Physical Layer that make reliable high-speed communication impossible without encoding.

📋 Three Problems 8b/10b Solves

8b/10b encoding was designed in the early 1980s for fibre channel and adopted by many high-speed serial standards including PCIe Gen 1 and Gen 2. It solves all three raw binary problems simultaneously through a single encoding transformation:

• DC balance. Every 10-bit encoded symbol has at most 6 ones and at least 4 ones (or at most 6 zeros). The encoding alternates between symbols that have more ones and symbols that have more zeros, keeping the running average of ones vs zeros close to 50%. This prevents the AC coupling capacitors from drifting. The mechanism is called Running Disparity.
• Transition density. The encoding guarantees that no more than five consecutive bits of the same polarity can appear in the serial stream — even across the boundary between two adjacent symbols. This ensures the receiver’s CDR always has a transition to lock onto at least every five bit times.
• Error detection. Of the 1024 possible 10-bit patterns, only 512 are valid encoded symbols for data, and many fewer for control characters. Any transmission error that creates an invalid pattern is immediately detectable at the receiver as a code violation.

📋 How 8b/10b Works

8b/10b takes an 8-bit input byte and produces a 10-bit output symbol. The transformation is not a straightforward expansion — it is a split encoding: the 8-bit input is divided into a 5-bit sub-block and a 3-bit sub-block, each encoded separately.

Each 5-bit sub-block has two possible encodings: one with more ones (positive disparity) and one with more zeros (negative disparity). Some sub-blocks have only one encoding — their encoding is disparity-neutral and looks the same regardless of CRD. The encoder selects between the two options to maintain DC balance.

📋 Character Notation — Dxx.y and Kxx.y

8b/10b uses a shorthand notation for naming characters. The 8-bit input byte is described in a specific format rather than just its hex value:

This notation uniquely identifies every 8b/10b character. There are 256 data characters (D0.0 through D31.7) and 12 defined control (K) characters. Not all Dxx.y combinations are legal — some are reserved or used only with specific disparity states.

📋 Disparity and the CRD

Disparity refers to the imbalance of ones versus zeros within a 10-bit symbol. A symbol with more ones than zeros has positive disparity (+). A symbol with more zeros has negative disparity (–). A symbol with equal ones and zeros has neutral disparity.

The Current Running Disparity (CRD) is a single bit maintained by both transmitter and receiver. It tracks the ongoing balance of ones and zeros in the serial stream. The CRD starts at either + or – and flips each time a non-neutral symbol is sent.

📋 CRD Rules and Encoding Choice

The CRD drives the encoding choice. The transmitter and receiver independently track the same CRD state — they stay synchronised because they apply the same rules to the same symbol stream. If they ever disagree, a disparity error is flagged.

The rule is simple: the disparity of each symbol must be opposite to or neutral with respect to the current CRD. Sending a positive-disparity symbol when CRD is already positive would make the link more unbalanced — that encoding is illegal and would never be produced by a correct encoder.

▶ Worked Encoding Example

Let’s encode the byte 0x6A (D10.3) with CRD = negative. The 5-bit sub-block EDCBA = 01010 (decimal 10) and the 3-bit sub-block HGF = 011 (decimal 3).

📋 Properties of a Legal Symbol

A 10-bit symbol produced by correct 8b/10b encoding always satisfies all of the following constraints. Any received symbol violating these is an immediate code violation error:

• The symbol contains 4, 5, or 6 ones — never fewer than 4 or more than 6. (This ensures disparity never exceeds ±2 per symbol.)
• The symbol never has more than five consecutive bits of the same polarity — neither within one symbol nor spanning the boundary from one symbol to the next.
• The 6-bit sub-block (abcdei) contains no more than four ones or four zeros.
• The 4-bit sub-block (fghj) contains no more than three ones or three zeros.
• The symbol must map to a valid 8-bit character in the data lookup table (D table) or control lookup table (K table). Patterns that don’t appear in either table are illegal.

Of the 2¹⁰ = 1024 possible 10-bit patterns, the encoding uses only 512 as valid data symbol encodings (2 per byte × 256 bytes). Adding the K-code symbols brings the total to approximately 530 valid patterns. The remaining 494+ are illegal and instantly detectable as transmission errors.

📋 Special Control Symbols (K-Codes)

Besides the 256 data characters (D-codes), 8b/10b defines 12 special control characters called K-codes. K-codes do not represent data bytes — they are used for link management, framing, and ordered set signalling. The receiver distinguishes K-codes from D-codes because K-codes map to their own separate lookup table.

📋 Ordered Sets

An ordered set is a specific sequence of symbols sent simultaneously on all active lanes at the same time. Ordered sets always begin with the COM (K28.5) symbol on every lane, followed by additional symbols that define the specific ordered set type. They are called “ordered” because their structure is tightly defined — the receiver can identify them by pattern, not just by header.

Key ordered sets in PCIe Gen 1/2:

• Training Sequence 1 (TS1) — used during link training to negotiate speed, link width, and lane numbers
• Training Sequence 2 (TS2) — follows TS1 to confirm training parameters before transitioning to L0
• SKIP Ordered Set (SOS) — COM followed by three SKP symbols, sent every 1180–1538 symbol times for clock compensation
• Electrical Idle Ordered Set (EIOS) — COM followed by three IDL symbols, signals receiver to prepare for electrical idle
• FTS Ordered Set — COM followed by three FTS symbols, sent by transmitter to exit L0s back to L0
• Electrical Idle Exit Ordered Set (EIEOS) — K28.7 repeated, provides low-frequency detectable signal for exiting electrical idle at Gen 2 speeds

📋 Error Detection — Code Violations and Disparity Errors

8b/10b provides Physical Layer error detection through two complementary mechanisms. Neither is as strong as the LCRC (which covers the full TLP), but they catch errors that LCRC cannot — specifically errors within the Physical Layer itself before bits are assembled into TLPs.

Code violations

Any received 10-bit symbol that does not appear in either the D-code or K-code lookup tables is a code violation. Immediately detectable. Causes: signal corruption on the link, loss of symbol lock, bit errors that happen to create an unrecognised pattern.

• Any 10-bit symbol containing more than six ones or more than six zeros
• Any 6-bit sub-block with more than four ones or four zeros
• Any 4-bit sub-block with more than three ones or three zeros
• Any symbol with more than five consecutive bits of the same polarity
• Any 10-bit pattern not in the defined lookup tables

Disparity errors

The receiver maintains its own CRD alongside the transmitter’s CRD. After receiving each symbol, the receiver checks that the symbol’s disparity is consistent with the current CRD value. If a transmitted symbol had a positive disparity and the receiver’s CRD was already positive, this is a disparity error — it could not have been produced by a correct encoder.

📋 The 20% Overhead

For every 8 bits of useful data, the transmitter sends 10 bits on the wire. The overhead is exactly 2/10 = 20%. This is significant and directly reduces the usable data throughput of the link.

The 20% overhead means that a Gen 1 x16 link with 2.5 GT/s per lane has a peak data throughput of 2.5 GT/s × 0.8 × 16 lanes / 8 bits per byte = 4000 MB/s = ~3.9 GB/s. The 20% is the primary reason PCIe Gen 3 abandoned 8b/10b entirely in favour of the far more efficient 128b/130b encoding.

📋 Scrambling — Why It Accompanies 8b/10b

Even with 8b/10b balancing ones and zeros, repetitive data patterns can produce periodic spectral peaks in the transmitted bitstream. For example, transmitting a long sequence of 0x55 bytes would create a regular alternating 1-0-1-0 pattern — a single strong frequency component that creates EMI and may stress PLL clock recovery circuits.

The Physical Layer scrambles data bytes before 8b/10b encoding by XORing them with a pseudo-random sequence generated by a Linear Feedback Shift Register (LFSR). The scrambling sequence is deterministic — both transmitter and receiver use the same LFSR initialised to the same value — so the receiver can trivially descramble by applying the same XOR sequence again. Scrambling spreads the spectral energy evenly across frequencies, eliminating strong periodic tones.

• Data bytes are scrambled. K-code control characters are not scrambled.
• The LFSR is reset (re-synchronised) at every COM character in Gen 1/2 — the unscrambled COM pattern is how the receiver knows to reset its own descrambler LFSR to the same initial state.
• Scrambling does not affect the 8b/10b DC balance or transition density guarantees — the LFSR output is itself pseudo-random with roughly equal ones and zeros.

⚡ Gen 3 Onwards — 128b/130b Replaces 8b/10b

Starting with Gen 3 (8 GT/s), PCIe abandoned 8b/10b encoding entirely. The 20% overhead was simply too costly as data rates increased. Gen 3 introduced 128b/130b encoding — a fundamentally different approach that achieves the same goals with only ~1.54% overhead.

How 128b/130b is different

Instead of encoding individual bytes, 128b/130b groups 128 data bits together as a single block and prepends a 2-bit sync header. The header encodes exactly two states: 01 meaning “this is a data block” and 10 meaning “this is an ordered set block”. DC balance is achieved entirely through scrambling — there is no CRD mechanism. K-codes and the COM character are no longer used for framing — the sync header replaces them. SKP ordered sets are still used for clock compensation, but their encoding changes. There is no longer a single special character for symbol lock — block alignment is achieved differently.

This is why Gen 3 hardware is more complex than Gen 1/2: the scrambler is more sophisticated (24-bit LFSR vs 16-bit), the framing detection is different, and equalization is mandatory rather than optional. The reward is nearly 100% efficiency instead of 80%.

📋 Quick Reference