Compiler Directives, Hierarchical Access & UDPs — VLSI Trainers Verilog Series · Module 18 Compiler Directives, Hierarchical Access & UDPs Complete coverage of all Verilog compiler directives, hierarchical naming and access techniques, and User-Defined Primitives (UDPs) — combinational and sequential — with full truth table notation. 📋 Contents Compiler Directives — Introduction `timescale `define / […]
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System Tasks, Functions & File I/O — VLSI Trainers Verilog Series · Module 17 System Tasks, Functions & File I/O Complete reference for Verilog’s built-in system tasks and functions — display, simulation control, math, conversion, random — and the full set of file-based I/O tasks for reading and writing files during simulation. 📋 Contents Introduction
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System Tasks, Functions & Compiler Directives — VLSI Trainers Verilog Series · Module 16 System Tasks, Functions & Compiler Directives Complete coverage of Verilog parameters (module and specify), path delays in the specify block, and the full set of compiler directives — with annotated diagrams and practical examples throughout. 📋 Contents Introduction Parameters — Introduction
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Switch Level — Delays, Strengths & Trireg — VLSI Trainers Verilog Series · Module 15 Switch Level — Delays, Strengths & Trireg Complete coverage of time delays in switch primitives, instantiation with explicit drive strengths and delays, and how the simulator resolves strength contention — especially with capacitive trireg nets. 📋 Contents Time Delays —
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Switch Level Modelling — VLSI Trainers Verilog Series · Module 14 Switch Level Modelling The lowest abstraction level in Verilog — model circuits at the MOS transistor level using nmos, pmos, cmos, and bidirectional switch primitives with truth tables, circuit diagrams, and complete examples. 📋 Contents Introduction Where Switch Level Fits Basic Transistor Switches nmos
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Behavioral Modelling Part 4 — While, Forever, Parallel, Force-Release, Events — VLSI Trainers Verilog Series · Module 13 Behavioral Modelling — Part 4 Complete coverage of while loops, forever loops, parallel blocks (fork-join), the force-release construct, and Verilog events — with practical RTL and testbench examples throughout. 📋 Contents while Loop — Introduction while Execution
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Behavioral Modelling Part 3 — if, assign-deassign, repeat, for, disable — VLSI Trainers Verilog Series · Module 12 Behavioral Modelling — Part 3 Deep coverage of if/if-else constructs, assign-deassign, the repeat construct, for loops, and the disable statement — with complete synthesizable and testbench examples. 📋 Contents if / if-else — Introduction Syntax & Forms
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Behavioral Modelling Part 2 — VLSI Trainers Verilog Series · Module 11 Behavioral Modelling — Part 2 Assignments with delays, the wait construct, multiple always blocks, complete RTL designs, blocking vs non-blocking deep-dive, the case statement family, and the Verilog simulation flow. 📋 Contents Assignments with Delays Three Delay Forms The wait Construct Multiple Always
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Behavioral Modelling in Verilog — VLSI Trainers Verilog Series · Module 10 Behavioral Modelling in Verilog The highest level of abstraction in Verilog — describe what a circuit does using procedural constructs, blocking and non-blocking assignments, and the full power of initial and always blocks. 📋 Contents Introduction Operations & Assignments Blocking Assignments Non-Blocking Assignments
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Modelling at Data Flow Level — VLSI Trainers Verilog Series · Module 09 Modelling at Data Flow Level Master Verilog’s continuous assignment model — how signals are driven, how delays are specified, how vectors are assigned, and every operator available at the data-flow level. 📋 Contents Introduction Data Flow vs Gate Level Continuous Assignment Structures
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