RS latch with NOR and NAND gates — race analysis — clocked RS — D flip-flop — JK flip-flop and race-around — Master-Slave JK — edge-triggered T flip-flop — asynchronous PRESET/CLEAR — excitation tables — flip-flop conversion with worked examples.
In combinational circuits (DE-05, DE-06), outputs depend only on current inputs. Sequential circuits add memory — the output depends on both current inputs and past history. The basic memory element storing one bit is the flip-flop.
The RS latch is the simplest memory element — two cross-coupled NOR gates where each gate’s output feeds back to the other’s input. S = Set (forces Q=1), R = Reset (forces Q=0). The outputs Q and Q̄ are always complements — except in the forbidden state.
When the RS latch transitions between states, both gates must change simultaneously — but propagation delays differ. This causes a race between the two flip-flop transitions.
| Race type | Cause | Outcome | Acceptable? |
|---|---|---|---|
| Valid (non-critical) race | RS changes from 10 or 01 to 00 — both gates race, but both paths lead to the same stable state | Predictable — same stable state regardless of which gate wins | Yes ✓ |
| Critical race | RS changes from 11 to 00 — one path reaches stable A (Q=0,Q̄=1) and another reaches stable B (Q=1,Q̄=0) | Unpredictable — outcome depends on inherent gate delays, which the designer cannot control | No ✗ |
Applying De Morgan’s theorem to the NOR latch gives an equivalent NAND latch. Two cross-coupled NAND gates with NOT gates on the inputs produce an active-HIGH RS latch — identical characteristic table to the NOR version, forbidden state still S=R=1.
Without the input inverters, the NAND latch has active-LOW S̄ and R̄ inputs. The characteristic table is inverted: S̄=R̄=1 is the HOLD state; S̄=0,R̄=1 SETs; S̄=1,R̄=0 RESETs; S̄=R̄=0 is the forbidden state.
| S̄ | R̄ | Q(n+1) | Mode |
|---|---|---|---|
| 1 | 1 | Q(n) | HOLD |
| 0 | 1 | 1 | SET (Q=1) |
| 1 | 0 | 0 | RESET (Q=0) |
| 0 | 0 | FORBIDDEN — both outputs go HIGH | |
This active-low NAND latch is the core of all TTL flip-flop ICs — the PRESET and CLEAR asynchronous inputs are active-low precisely because of this latch topology.
Adding two AND gates (or NAND gates) in front of the latch creates a synchronous flip-flop — the latch only responds to inputs when the clock (CLK) is HIGH. When CLK=0 the AND gates block R and S, holding the latch in HOLD mode regardless of input changes.
Two different ways to determine when a flip-flop samples its inputs:
| Type | When FF responds | Symbol on CLK pin | Problem |
|---|---|---|---|
| Level-triggered | Output can change any time CLK is HIGH (or LOW) | No symbol | Multiple transitions possible during one clock pulse |
| Positive edge-triggered | Only on LOW→HIGH transition (rising edge) | Small triangle ▷ | None — inputs must be stable only around the edge |
| Negative edge-triggered | Only on HIGH→LOW transition (falling edge) | Triangle with bubble ▷○ | None |
A narrow spike at the rising edge is generated by: feed CLK through a NOT gate (propagation delay d), then AND the original CLK with the delayed inverted CLK. The AND output is HIGH only for those few nanoseconds when both CLK=1 and CLK̄=1 simultaneously — exactly the propagation delay of the inverter, typically 5–10 ns.
The D (Data/Delay) flip-flop is a modified clocked RS flip-flop that eliminates the forbidden state by tying S=D and R=D̄ — the two inputs are always complements. Only one external input D is needed.
The JK flip-flop is a modified RS flip-flop where J≡S and K≡R, but the outputs are fed back to the AND gates. This means when J=K=1, the latch toggles — eliminating the forbidden state entirely.
| J | K | Q(n+1) | Mode |
|---|---|---|---|
| 0 | 0 | Q(n) | HOLD |
| 0 | 1 | 0 | RESET |
| 1 | 0 | 1 | SET |
| 1 | 1 | Q̄(n) | TOGGLE (complement) |
Characteristic equation: Q(n+1) = J·Q̄(n) + K̄·Q(n)
When J=K=1 and CLK is HIGH, the output toggles → feedback changes inputs → toggles again → infinite loop during the clock pulse. This is the race-around condition. Two solutions:
The T flip-flop is the simplest sequential element — it has a single input T and toggles on every clock edge when T=1. Built by connecting J and K inputs of a JK flip-flop together to form one T input.
| T | Q(n+1) | Mode |
|---|---|---|
| 0 | Q(n) | HOLD (no change) |
| 1 | Q̄(n) | TOGGLE (complement) |
Key application — Frequency Division: If T=1 permanently, the flip-flop toggles on every clock edge. The Q output is exactly half the clock frequency: f_out = f_CLK / 2. Chain n T flip-flops to divide by 2ⁿ — the foundation of binary counters (DE-10).
In practical flip-flops, two additional inputs — PRE̅ (Preset) and CLR̅ (Clear) — allow the flip-flop to be set or reset immediately, independent of the clock. They operate asynchronously (no clock needed) and are typically active-LOW.
| PRE̅ | CLR̅ | Q | Q̄ | Action |
|---|---|---|---|---|
| 1 | 1 | Normal JK operation | Clock controls output | |
| 0 | 1 | 1 | 0 | PRESET — sets Q=1 immediately |
| 1 | 0 | 0 | 1 | CLEAR — resets Q=0 immediately |
| 0 | 0 | Undefined | FORBIDDEN — both outputs try to be 1 | |
Two JK flip-flops in series with complementary clocking: the Master is enabled when CLK=1; the Slave is enabled when CLK=0 (CLK=1 disables Slave). Because the Slave is disabled while the Master is active, the Master’s output cannot feed back and cause race-around.
The characteristic table tells you next state given inputs and current state. The excitation table is the inverse — it tells you what inputs are required to achieve a given transition from Q(n) to Q(n+1). Excitation tables are essential for sequential circuit design and flip-flop conversion.
| Q(n) | Q(n+1) | S | R |
|---|---|---|---|
| 0 | 0 | 0 | φ |
| 0 | 1 | 1 | 0 |
| 1 | 0 | 0 | 1 |
| 1 | 1 | φ | 0 |
| Q(n) | Q(n+1) | J | K |
|---|---|---|---|
| 0 | 0 | 0 | φ |
| 0 | 1 | 1 | φ |
| 1 | 0 | φ | 1 |
| 1 | 1 | φ | 0 |
| Q(n) | Q(n+1) | D |
|---|---|---|
| 0 | 0 | 0 |
| 0 | 1 | 1 |
| 1 | 0 | 0 |
| 1 | 1 | 1 |
| Q(n) | Q(n+1) | T |
|---|---|---|
| 0 | 0 | 0 |
| 0 | 1 | 1 |
| 1 | 0 | 1 |
| 1 | 1 | 0 |
Any flip-flop type can be converted to any other type by adding a combinational circuit at the input that translates the required flip-flop’s input signals into the given flip-flop’s inputs. The method uses both excitation tables.
We have a JK FF and want it to behave as an RS FF. From the RS excitation table, find what J and K must be for each RS transition:
We have a D FF and want JK behaviour. For each JK input combination and Q(n), what D input is needed to achieve Q(n+1)?
The combinational circuit D = J·Q̄ + K̄·Q is added between the JK inputs and the D flip-flop input. This is a 2-gate circuit: one AND-OR network with Q and Q̄ feedback.
| Parameter | Symbol | Definition | Importance |
|---|---|---|---|
| Propagation delay (clock→Q) | t_PLH, t_PHL | Time from triggering clock edge to output transition (measured at 50% levels) | Limits maximum clock frequency |
| Set-up time | t_s | Minimum time data must be stable BEFORE the triggering clock edge | Violated = setup time violation → metastability |
| Hold time | t_h | Minimum time data must remain stable AFTER the triggering clock edge | Violated = hold time violation → metastability |
| Maximum clock frequency | f_max | Maximum clock rate at which FF operates reliably | Determines system speed limit |
| Minimum pulse width | t_CH, t_CL | Minimum HIGH time and minimum LOW time for the clock pulse | Specified in datasheet — must not be violated |
| Async PRESET/CLEAR delay | t_PLH (PRE), t_PHL (CLR) | Time from asynchronous input active to output responding | Determines initialisation speed |
| FF Type | Char. Equation | Forbidden / Special | Key Use |
|---|---|---|---|
| RS (NOR) | Q(n+1) = S + R̄·Q(n) | S=R=1 forbidden (both Q=0) | Basic latch, input stage |
| RS (NAND, active-low) | Q(n+1) = S̄’+ R̄’·Q̄(n) | S̄=R̄=0 forbidden (both Q=1) | TTL internal latches |
| D | Q(n+1) = D | None — no forbidden state | Data registers, pipeline |
| JK | Q(n+1) = J·Q̄ + K̄·Q | J=K=1 → toggle (no forbidden) | Universal — counters, registers |
| T | Q(n+1) = T⊕Q(n) | T=1 → toggle; T=0 → hold | Counters, frequency dividers |
| Conversion | Combinational logic needed |
|---|---|
| JK → RS | J = S K = R |
| D → JK | D = J·Q̄ + K̄·Q |
| JK → D | J = D K = D̄ |
| JK → T | J = T K = T |