Learn advanced combinational circuits in digital electronics — multiplexers, demultiplexers, decoders, encoders, comparators, parity generator/checker, code converters, and programmable logic devices like FPLA, PAL, and PROM.
Learn combinational switching circuits in digital electronics — Half Adder, Full Adder, subtractors, BCD and Excess-3 adders, 2’s complement adder/subtractor, truth tables, Boolean expressions, K-map derivations, and IC references.
Combinational Logic Design Tutorial with Examples Read More »
Learn simplification of Boolean functions using Karnaugh Maps (2–6 variables), pairs, quads, octets, rolling and overlapping groups, don’t-care conditions, NOR realization, and the Quine-McCluskey method.
Learn Boolean Algebra and Logic Gates in digital electronics — AND, OR, NOT operations, Huntington’s postulates, Boolean theorems, De Morgan’s law, SOP/POS forms, Venn diagrams, and NAND/NOR realization.
Learn binary codes in digital electronics — BCD, weighted and self-complementing codes, Gray code, Excess-3 arithmetic, parity checking, Hamming error correction, CRC, ASCII, and EBCDIC with examples.
Learn number systems in digital electronics — positional systems, radix conversions, binary arithmetic, signed numbers using 1’s and 2’s complement, multiplication, division, and floating-point representation with examples.
Learn Digital Electronics through a complete 12-article series covering number systems, Boolean algebra, logic gates, combinational and sequential circuits, flip-flops, counters, and digital memories with diagrams and examples.
Digital Electronics — Complete 12-Article Series Read More »
PCIe Series — PCIe-07: Completion TLPs — VLSI Trainers PCIe Series · PCIe-07 Completion TLPs The full Cpl and CplD header — Completer ID, Status codes, Byte Count, Lower Address, Requester ID, and Tag — plus split-completion mechanics, Completion Timeout, CplLk/CplDLk for locked transactions, and what none of this changes in Gen 6. Contents What
PCIe Series — PCIe-06: Memory Read and Write TLPs — VLSI Trainers PCIe Series · PCIe-06 Memory Read and Write TLPs Full bit-level headers for MRd, MWr, and MRdLk — 3DW and 4DW variants side by side, Requester ID, Tag, Byte Enables explained with worked examples, address rules, the 4 KB boundary constraint, and how
PCIe Series — PCIe-05: TLP Structure — Common Header Fields — VLSI Trainers PCIe Series · PCIe-05 TLP Structure — Common Header Fields Every TLP starts with the same first Doubleword. This post dissects it bit by bit — Fmt, Type, TC, LN, TH, TD, EP, Attr (RO, NS, IDO), AT, and Length — with
