Understanding RTL, DTL, TTL, ECL and CMOS Logic Families

📐 Logic Family Parameters

Before comparing logic families we must define the six parameters used for comparison. All are measurable from the device datasheet.

Fan-in

Maximum number of inputs a single logic gate can accept. A 3-input AND gate has fan-in = 3. Exceeding fan-in degrades logic levels.

Fan-out

Number of identical gates a single gate output can reliably drive without violating voltage/current specs. A fan-out of 10 means one output can drive 10 gate inputs.

Propagation Delay (t_pd)

Time from input change to output change, measured at 50% voltage levels. Average of t_PHL and t_PLH. Smaller = faster gate.

t_pd = (t_PHL + t_PLH) / 2

Power Dissipation

Power consumed per gate = V_CC × I_CC. Ranges from microwatts (CMOS static) to milliwatts (ECL). Speed × Power = Figure of merit (lower is better).

Operating Temperature

Commercial: 0°C to +70°C (74-series). Military: –55°C to +125°C (54-series). Same electrical spec, wider temperature range.

Noise Margin

Maximum noise voltage that can be tolerated without causing incorrect logic operation. Defined separately for HIGH state (V_NH) and LOW state (V_NL).

📊 Noise Margin in Detail

Noise margin quantifies how much noise can be added to a signal before the receiving gate interprets it incorrectly. Four voltage levels define the boundaries:

Figure 1 — Noise margin voltage bands. The driver must output voltages outside the forbidden zone; the receiver must accept all valid driver outputs. Noise voltage less than V_NH or V_NL will not cause errors. CMOS has much wider margins than TTL — up to 30–45% of V_DD.

Higher noise margin = more robust. HTL was designed specifically for industrial environments with high electrical noise — its 15V supply gives noise margins of about 7V. CMOS is next best with ~30% V_DD margin. Standard TTL (0.4V) is marginal in noisy environments.

⚡ RTL — Resistor-Transistor Logic

RTL is the earliest logic family. Each gate uses input resistors and a transistor — when any input resistor drives the transistor into saturation, the output goes LOW. The basic RTL gate is a NOR gate.

When both inputs A and B are LOW, transistors T₁ and T₂ are in cutoff → output HIGH (logic 1). When either input is HIGH, the corresponding transistor saturates → output LOW (logic 0). This is NOR operation.

RTL Advantages

Simplest circuit — few components
Low power dissipation per gate

RTL Disadvantages

Low noise margin
High propagation delay (~20 ns)
Now obsolete

⚡ DCTL — Direct Coupled Transistor Logic

DCTL is RTL with the base resistors removed — transistor bases connect directly to the driving collector. Very simple, but the missing base resistors cause current hogging: small transistor V_BE variations mean one transistor takes all the base current, leaving others starved. Very low noise margin and not suitable for production ICs. Essentially obsolete.

⚡ I²L — Integrated Injection Logic

Integrated Injection Logic (I²L or IIL) is a bipolar family designed for very high packing density. Each gate cell consists of a lateral PNP transistor (acting as a constant current source that “injects” current into the base) and a vertical NPN transistor (the logic switch).

When the input is LOW (grounded): injected current is diverted to ground — NPN transistor is in cutoff → output HIGH
When the input is HIGH: injected current flows into NPN base → NPN saturates → output LOW

Why I²L matters. The basic cell occupies minimal silicon area — no resistors, no isolation between cells. This made I²L the dominant technology for LSI digital functions (early microprocessors, calculators) before CMOS became dominant. The entire gate is just two transistors sharing a base/emitter region.

⚡ DTL — Diode-Transistor Logic

DTL uses input diodes (D₁, D₂) for the logic AND function and a transistor (T₁) for inversion, producing a NAND gate. An additional diode D₃ in series with the transistor base ensures T₁ stays in cutoff when inputs are LOW, by requiring a higher turn-on voltage.

Inputs LOW → D₁,D₂ forward biased → point P at ~0.7V → insufficient to overcome D₃ + V_BE → T₁ cutoff → output HIGH
Inputs HIGH → D₁,D₂ reverse biased → V_P rises → D₃ conducts → T₁ saturates → output LOW (≈0.2V)

The resistor R₂ between base and ground speeds up transistor turn-off by removing stored charge. Propagation delay ≈ 50 ns, noise margin is good. Now replaced by TTL.

🏭 HTL — High-Threshold Logic

HTL is a modified DTL designed for industrial environments with severe electrical noise. It uses a 15V supply and a Zener diode (V_Z = 6.9V) in place of D₃. The transistor T₂ only conducts when the emitter of T₁ reaches 7.5V (= 6.9V + V_BE,T₂ ≈ 0.6V).

Output LOW ≈ 0.2V, output HIGH ≈ 15V. Noise margin ≈ 7V — far larger than any other family. The trade-off is speed: HTL is the slowest saturated logic family. Used in relay-replacement and PLC applications where noise immunity matters more than speed.

🔵 TTL — Transistor-Transistor Logic

TTL is the most widely used bipolar logic family. It replaces the DTL input diode array with a multi-emitter transistor — a single BJT whose multiple emitters each act as one input diode. This speeds up turn-off by actively pulling base charge away through T₁’s collector-base junction.

Figure 2 — Standard TTL NAND gate. The multi-emitter transistor T₁ replaces the DTL input diodes for faster switching. T₂ is the phase splitter that drives the totem-pole (T₃+T₄+D) output stage. The totem-pole provides low output impedance in both states, giving high fan-out.

TTL Series — Speed vs Power Trade-offs

54L / 74L

Low power

33 ns delay

1 mW/gate

54 / 74

Standard

10 ns delay

10 mW/gate

54H / 74H

High speed

6 ns delay

22 mW/gate

54S / 74S

Schottky

3 ns delay

19 mW/gate

54LS / 74LS

Low-pwr Schottky

10 ns delay

2 mW/gate

74 vs 54 series. Both series have identical circuit designs and electrical specifications. The 54-series operates from –55°C to +125°C (military grade) with tighter V_CC tolerance (4.5V–5.5V). The 74-series is commercial grade (0°C to +70°C). Always use the 54-series for aerospace, military, and high-reliability applications.

TTL Logic Levels

Parameter	Value	Meaning
VOH(min)	2.4 V	Minimum guaranteed HIGH output — any valid logic 1 output is ≥ 2.4V
VOL(max)	0.4 V	Maximum guaranteed LOW output — any valid logic 0 output is ≤ 0.4V
VIH(min)	2.0 V	Minimum input to be recognised as logic 1
VIL(max)	0.8 V	Maximum input to be recognised as logic 0
V_NH	0.4 V	HIGH-state noise margin = VOH(min) − VIH(min) = 2.4 − 2.0
V_NL	0.4 V	LOW-state noise margin = VIL(max) − VOL(max) = 0.8 − 0.4

🔧 TTL Variants: Open-Collector and Tri-State

Open-Collector TTL

In open-collector gates, the upper totem-pole transistor (T₃) is omitted. The output is the collector of the lower transistor T₄ — left floating (open). An external pull-up resistor to V_CC must be added by the designer to get a proper HIGH output.

Figure 3 — Wire-AND with open-collector gates. Three outputs share one pull-up resistor. If any output transistor saturates, the common line is pulled LOW. Only when all transistors are off does R pull the line HIGH. Totem-pole outputs cannot be wire-ANDed — they would short-circuit.

Limitation of open-collector gates. They are slower than totem-pole gates because the HIGH state is driven only by the passive pull-up resistor R rather than by an active transistor. The larger R is, the slower the rising edge (RC time constant). Tri-state gates (next) solve both the wire-AND and the speed problem together.

Tri-State (Three-State) TTL

Tri-state devices have three output states: HIGH, LOW, and high impedance (Hi-Z). In the Hi-Z state, the output is effectively disconnected — no current flows in or out. This allows multiple tri-state outputs to share a common bus.

ENABLE = HIGH: circuit operates as normal inverter/gate
ENABLE = LOW: diode D₁ forward biases → steals base current from T₃; simultaneously T₂ turns off → T₄ turns off. Both T₃ and T₄ are in cutoff → output is Hi-Z (floating)

Bus connection rule. Only ONE tri-state driver must have its Enable asserted at any time. All others must be in Hi-Z. This is the foundation of data-bus architecture in all microprocessors — the address/data bus uses tri-state buffers so any device can drive the bus, while all others step aside.

⚡ Schottky TTL (STTL)

Standard TTL transistors saturate during operation — when switching from saturation to cutoff, the stored base charge must first be removed. This storage time limits switching speed. Schottky TTL prevents saturation by placing a Schottky Barrier Diode (SBD) between the base and collector of each transistor.

The SBD has a forward voltage of only 0.25V. When the transistor approaches saturation (V_CE approaches 0), the SBD turns on and clamps V_CE at approximately 0.4V — just above saturation. The transistor never fully saturates, so there is no stored charge to remove, drastically cutting switching time.

Series	t_pd	Power/gate	Notes
74S	3 ns	19 mW	Schottky — fastest TTL, but high power
74LS	10 ns	2 mW	Low-power Schottky — same speed as 74, 1/5 the power — the workhorse of TTL
74ALS	4 ns	1 mW	Advanced LS — best combination of speed and power in TTL era

🔴 ECL — Emitter Coupled Logic

ECL is the fastest logic family — transistors never saturate, eliminating storage time entirely. The circuit is a differential amplifier: transistors switch between the active and cutoff regions, never entering saturation.

Figure 4 — ECL gate architecture. The reference transistor T₅ is biased at –1.29V. When an input exceeds this threshold, current shifts from T₅ to the input transistor, generating both OR and NOR outputs simultaneously. The emitter-follower output stages (T₇, T₈) provide low output impedance.

🟡 MOS Logic — NMOS and PMOS

MOS logic uses MOSFETs instead of bipolar transistors. No biasing resistors are needed — the load transistor T₁ (with gate tied to drain) acts as a resistor. MOS circuits are simpler to fabricate and have higher packing density than bipolar logic.

NMOS (N-channel)

Enhancement N-channel MOSFETs. Operates with positive supply (+V_DD). Gate positive w.r.t. source → conduction (logic 1). Gate at 0V → OFF.

NOR gate: T₂, T₃, T₄ in parallel — any HIGH input turns on a transistor → output LOW.
NAND gate: T₂, T₃, T₄ in series — all HIGH needed for output LOW.

PMOS (P-channel)

Enhancement P-channel MOSFETs. Operates with negative supply (–V_DD). Gate negative w.r.t. source → conduction. Works with negative logic — complements of NMOS inputs/outputs.

Same circuit topology as NMOS but all supply polarities and logic levels inverted.

MOS advantages: high packing density, no resistors needed, low static power, high fan-out (>20). Disadvantage: slower than bipolar families (400 ns propagation delay) and susceptible to gate oxide damage from static discharge.

🟢 CMOS — Complementary MOS

CMOS uses complementary pairs of PMOS and NMOS transistors. The key insight: in steady state, one transistor is always OFF — so no DC current path exists from V_DD to ground. Static power dissipation is essentially zero (only leakage current). Power is only consumed during switching.

Figure 5 — CMOS gate structures. In the NAND: PMOS transistors in parallel (any LOW input keeps output HIGH); NMOS in series (BOTH HIGH needed for LOW output). In the NOR: PMOS in series (BOTH LOW needed for HIGH); NMOS in parallel (ANY HIGH gives LOW output). One transistor set is always OFF — zero DC current path.

CMOS Advantages

Near-zero static power dissipation — ideal for battery-powered devices
Wide supply range: 3V to 15V (4000 series) or 2V to 6V (74HC series)
Very high noise margin: ~30% of V_DD (e.g. 1.5V at 5V supply vs TTL’s 0.4V)
Very high fan-out: >50 (MOSFET inputs draw no DC current)
High packing density: basis of all modern VLSI — billions of CMOS transistors per chip

CMOS dynamic power. Although static power is near zero, CMOS consumes power during switching: P = C·V²·f (capacitance × voltage² × frequency). At GHz clock rates in modern processors, this becomes significant — which is why reducing V_DD (voltage scaling) is the primary technique for reducing power in modern chips, even at the cost of noise margin.

📊 Full Family Comparison Table

All values are typical; actual figures depend on specific IC revision. The 54/74 standard TTL is the reference baseline.

Parameter	RTL	DTL	TTL (74)	Schottky (74S)	ECL	MOS	CMOS
Basic gate (+ve logic)	NOR	NAND	NAND	NAND	OR/NOR	NAND	NAND/NOR
Max fan-in	5	10	8	8	5	8	8
Fan-out	5	8	10	10	25	20	>50
Power dissipation (mW/gate)	12	10	10	19	300	2	0.01 static
Propagation delay (ns)	20	30–50	10	3	1	400	70
Noise immunity	Nominal	Good	Very good	Very good	Good	Nominal	Very good
Clock rate (MHz)	5	12	15	100+	300+	2	5
Supply voltage	+3.6V	+5V	+5V	+5V	–5.2V	+5 to –5V	3–15V
Status	Obsolete	Obsolete	Legacy	Legacy	Niche (RF/HF)	Obsolete	Dominant

Modern reality. CMOS has completely dominated digital IC design since the 1990s. Sub-micron CMOS offers ECL-like speeds at a fraction of the power. Every microprocessor, FPGA, memory chip, and SoC today is implemented in CMOS. ECL survives only in ultra-high-speed RF and optical communications circuits where its 1 ns delay is still unmatched by standard CMOS.

📋 Quick Reference

Family	Key feature	Basic gate	Speed	Power
RTL	Resistors + transistors. Simplest. Obsolete.	NOR	Slow (20ns)	Low
DCTL	RTL without base resistors. Current hogging problem.	NOR	Slow	Low
I²L	PNP current injector + NPN switch. High density LSI.	NOR	Medium	Very low
DTL	Input diodes + transistor. Good noise margin. Obsolete.	NAND	Slow (50ns)	Medium
HTL	Modified DTL. 15V supply. 7V noise margin. Industrial.	NAND	Very slow	High
TTL	Multi-emitter transistor. Totem-pole output. Workhorse.	NAND	10 ns	10 mW
STTL	Schottky diode prevents saturation. Fastest TTL.	NAND	3 ns	19 mW
74LS	Low-power Schottky. Best TTL power-speed product.	NAND	10 ns	2 mW
ECL	Non-saturating differential amp. Fastest (1 ns).	OR/NOR	1 ns	300 mW
NMOS/PMOS	FET-based. Simple, high density. Slow. Obsolete.	NAND	400 ns	Low
CMOS	Complementary P+N pairs. Near-zero static power. Dominant.	NAND/NOR	70 ns→GHz	≈0 static

Noise margin formula	TTL values	CMOS typical
V_NH = VOH(min) − VIH(min)	2.4 − 2.0 = 0.4V	~1.5V at 5V
V_NL = VIL(max) − VOL(max)	0.8 − 0.4 = 0.4V	~1.5V at 5V
Figure of merit	Speed (ns) × Power (mW) — lower is better

Coming next — DE-08: Flip-Flops — the basic memory elements of all sequential circuits. RS latch with NOR and NAND gates, race analysis, clocked RS, D flip-flop, JK flip-flop and the race-around condition, Master-Slave JK, edge-triggered T flip-flop, asynchronous PRESET/CLEAR inputs, excitation tables, and flip-flop conversion.

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