DE-11: DAC & ADC — VLSI Trainers Digital Electronics Series · DE-11 DAC & ADC Weighted-resistor and R-2R ladder DACs — performance criteria (resolution, accuracy, monotonicity, settling time) — IC DAC0808 — Flash, Successive Approximation (SAR), Counter-ramp, Single-slope, and Dual-slope ADCs — IC ADC0801 — with VLSI mixed-signal design perspective. Contents The Analog–Digital Interface Weighted […]
DE-10: Counters — VLSI Trainers Digital Electronics Series · DE-10 Counters Asynchronous ripple counters, synchronous binary counters, up/down counters, Mod-N design procedure, decade counters, arbitrary-sequence counters, counter ICs (7490, 7492, 7493, 74160, 74163, 74190) — and their role in VLSI clock dividers, scan chains, and timing control. Contents Counter Basics & VLSI Relevance Asynchronous (Ripple)
DE-09: Shift Registers — VLSI Trainers Digital Electronics Series · DE-09 Shift Registers SISO, SIPO, PISO, PIPO — Bidirectional and Universal shift registers — Ring counter and Johnson counter — IC details (7491, 74164, 74194, 74195) — Serial adder, parity generator, time delay, data conversion, and sequence generator applications. Contents What is a Register? Four
DE-08: Flip-Flops — VLSI Trainers Digital Electronics Series · DE-08 Flip-Flops RS latch with NOR and NAND gates — race analysis — clocked RS — D flip-flop — JK flip-flop and race-around — Master-Slave JK — edge-triggered T flip-flop — asynchronous PRESET/CLEAR — excitation tables — flip-flop conversion with worked examples. Contents Sequential Circuits &
DE-07: Logic Families — VLSI Trainers Digital Electronics Series · DE-07 Logic Families The electronic hardware behind every logic gate — RTL, DCTL, I²L, DTL, HTL, TTL (totem-pole, open-collector, tri-state), Schottky TTL, ECL, NMOS/PMOS, and CMOS — with fan-in, fan-out, propagation delay, noise margin, power dissipation, and the complete family comparison table. Contents Logic Family
DE-06: MUX, Decoders, Encoders, Comparators & PLDs — VLSI Trainers Digital Electronics Series · DE-06 More Combinational Circuits Multiplexers, Demultiplexers, Decoders (3-to-8, BCD-to-decimal, BCD-to-7-segment), Code Converters, Encoders, Priority Encoders, Magnitude Comparators, Parity Generator/Checker, and Programmable Logic Devices — FPLA, PAL, and PROM. Contents Multiplexers (MUX) MUX Expansion & Applications Implementing Boolean Functions with MUX Demultiplexers
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DE-05: Combinational Circuits — Adders & Subtractors — VLSI Trainers Digital Electronics Series · DE-05 Combinational Switching Circuits Combinational design methodology — Half Adder, Full Adder, Parallel Binary Adder, Half & Full Subtractor, BCD (8421) Adder, Excess-3 Adder, and the 2’s Complement Adder/Subtractor — with truth tables, Boolean expressions, K-map derivations, and IC references. Contents
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DE-04: K-Map Simplification — VLSI Trainers Digital Electronics Series · DE-04 Simplification of Boolean Functions Karnaugh maps from 2 to 6 variables — pairs, quads, octets, rolling, overlapping, and redundant groups — don’t-care conditions, NOR implementation using 0-grouping, and the Quine-McCluskey tabular method. Contents Why Simplify? 2-Variable K-Map 3-Variable K-Map 4-Variable K-Map Groups — Pairs,
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DE-03: Boolean Algebra & Logic Gates — VLSI Trainers Digital Electronics Series · DE-03 Boolean Algebra & Logic Gates AND, OR and NOT operations — Huntington’s postulates, Boolean theorems including De Morgan’s, Duality principle, Venn diagrams, SOP and POS canonical forms, and realization using NAND/NOR universal gates. Contents Logic Operations — AND, OR, NOT Huntington’s
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DE-02: Binary Codes — VLSI Trainers Digital Electronics Series · DE-02 Binary Codes BCD and weighted codes, self-complementing codes, Gray code, Excess-3 arithmetic, parity-based error detection, Hamming error correction, CRC, and alphanumeric codes — ASCII and EBCDIC. Contents BCD (8421) Code Weighted Codes Self-Complementing Codes Gray (Cyclic) Code Parity — Error Detection Hamming Code —
