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Up until now, we have discussed how packets are formed, prioritized, and delivered. But what happens when multiple transactions are moving through the PCIe fabric at the exact same time? How does the system decide which packet needs to stay in line, and which one is allowed to pass? In Lecture 17, we are diving […]

In Lecture 14, we saw how a single port decides which Virtual Channel (VC) gets to transmit first. But what happens when packets arriving from multiple different ingress ports all want to use the exact same outgoing Virtual Channel on an egress port? To prevent collisions and ensure fair access, PCI Express uses Port Arbitration.

In Lecture 13, we learned how Traffic Classes (TCs) are mapped to independent hardware buffers called Virtual Channels (VCs). But what happens if a device has more than one VC, and multiple VCs have packets ready to send at the exact same time? This is where Virtual Channel (VC) Arbitration comes into play. VC arbitration

In Lecture 12, we introduced the concept of Quality of Service (QoS) and Differentiated Services. But how does the PCIe fabric actually distinguish between high-priority packets and normal background traffic? In Lecture 13, we explore the software and hardware combination that makes QoS possible: Traffic Classes (TC) and Virtual Channels (VC). Part 1: Traffic Classes

Up until now, we have explored how packets are built and how flow control prevents congestion. But what happens when certain data packets are simply more important than others? In Lecture 12, we are introducing Quality of Service (QoS) and Differentiated Services. The Need for QoS Many general-purpose computer systems historically lacked mechanisms to manage

In Lecture 10, we examined the math that transmitters use to decide if a packet can be sent. But what happens when the receiver processes those packets and frees up its buffer space? In Lecture 11, we are going to explore how devices keep the Link running continuously by sending Flow Control Updates, how the

In Lecture 9, we discussed Flow Control initialization. Now, in Lecture 10, we are diving into the specific hardware elements—the counters and registers—inside the Transmitter and Receiver. We will also break down the exact math the system uses to calculate whether a pending Transaction Layer Packet (TLP) is allowed to cross the Link! To manage

In Lecture 8, we explored how Flow Control buffers are physically organized into Posted, Non-Posted, and Completion categories. But before a single Transaction Layer Packet (TLP) is ever allowed to cross the Link, the two connected devices must officially agree on how much buffer space is available. In Lecture 9, we are walking through the

In Lecture 7, we introduced the concept of the credit-based flow control mechanism that prevents Link congestion. Now, in Lecture 8, we are going to look under the hood at the specific architecture of the hardware buffers that make this system possible. Flow control buffers are implemented for each Virtual Channel (VC) resource supported by

Now that we understand how packets are built and routed, it is time to explore how PCI Express meticulously manages traffic. In Lecture 7, we are exploring Flow Control Concepts and how PCIe prevents traffic jams on the Link. The Problem with Legacy Buses In older parallel bus architectures like PCI, transactions were attempted blindly,