Test Your Digital Electronics Skills

Explanation: 1101 0110 = 128+64+0+16+0+4+2+0 = 214.

Explanation: 2F hex = 2×16 + 15 = 32 + 15 = 47.

Explanation: Correct. 1’s complement inverts all bits; 2’s complement adds 1 to the result. This makes 2’s complement arithmetic straightforward for subtraction.

Explanation: +45 = 0010 1101. 1’s complement = 1101 0010. Add 1 → 1101 0011. This is −45 in 8-bit 2’s complement.

Explanation: The defining property of Gray code is that exactly 1 bit changes between consecutive codewords. This is why it’s used in CDC FIFO pointers — a glitch during transition can only corrupt the value by ±1.

Explanation: Each octal digit → 3 binary bits. 3→011, 4→100, 7→111 → 011 100 111 = 9 binary digits.

Explanation: True. BCD represents each decimal digit (0–9) with its 4-bit binary pattern. Codes 1010–1111 are unused/illegal in BCD.

Explanation: Hamming condition: 2^r ≥ r + m + 1. For m=4: 2^3=8 ≥ 3+4+1=8. So r=3 parity bits are needed → total codeword = 7 bits.

Explanation: XS-3 = BCD + 0011. For 5: 0101 + 0011 = 1000.

Explanation: False — but the related true property is: the 1’s complement of an XS-3 codeword gives the XS-3 code of the 9’s complement of the original digit. This is XS-3’s self-complementing property.

Explanation: 0.101 binary = 1×2⁻¹ + 0×2⁻² + 1×2⁻³ = 0.5 + 0 + 0.125 = 0.625.

Explanation: IEEE 754 single precision (32-bit): 1 sign + 8 exponent + 23 mantissa. The 8-bit exponent uses a bias of 127.

Explanation: True. De Morgan’s first theorem: (A+B)’ = A’·B’. The second: (A·B)’ = A’+B’. Together they allow any expression to be converted between NOR and NAND forms.

Explanation: By the absorption law: A + A·B = A(1+B) = A·1 = A.

Explanation: A K-map for n variables has 2ⁿ cells. For n=4: 2⁴=16 cells arranged in a 4×4 grid.

Explanation: A group of 2ⁿ cells eliminates n variables. A quad (4 = 2²) eliminates 2 variables, leaving 4−2=2 variables in the product term.

Explanation: True. K-maps are toroidally connected — top wraps to bottom and left wraps to right. This allows octets and quads that span the edges of the map.

Explanation: From the K-map: group {0,1,8,9} (B̄D̄), group {0,2,8,10} (B̄C̄), group {1,5} (ĀBD). F = B̄D̄ + B̄C̄ + ĀBD.

Explanation: Both NAND and NOR are universal gates — any logic function can be implemented using only NAND gates, or using only NOR gates. This is exploited when a single gate type is available in a technology.

Explanation: True. A minterm mᵢ is 1 for exactly one combination of variable values. For 3 variables A,B,C: m₅ = AB̄C (A=1,B=0,C=1). Minterms form the basis of SOP expressions.

Explanation: Two minterms differing in exactly one bit position can be combined, eliminating that variable. This is the tabular equivalent of grouping adjacent cells in a K-map.

Explanation: 2⁵ = 32 cells. A 5-variable K-map is typically drawn as two 4×4 sub-maps.

Explanation: The dual is formed by swapping AND↔OR and 0↔1 (but NOT complementing variables). A·(B+C̄) → A+(B·C̄). Variables remain unchanged.

Explanation: True. Don’t-care cells (marked X or d) can be assigned 0 or 1 at the designer’s discretion. When assigned 1, they can be grouped with actual 1s to form larger groups and reduce the minimised expression.

Explanation: Sum = A ⊕ B (XOR). Note that option D is the expanded form of XOR and is correct too — but option C is the standard minimal form.

Explanation: True. HA1 adds A+B → sum S, carry C. HA2 adds S+Cin → sum S_out, carry C’. The final carry Cout = C OR C’. Total: 2 HA + 1 OR.

Explanation: 0110 (decimal 6) is added to skip the six illegal BCD codes (1010–1111). The correction generates the correct BCD digit and a carry to the next position.

Explanation: An N:1 MUX needs log₂(N) select lines. For 4:1: log₂(4) = 2 select lines S₁, S₀.

Explanation: An n-bit flash ADC needs 2ⁿ−1 comparators. For 4 bits: 2⁴−1 = 15 comparators.

Explanation: True. Connect the Enable as data input and the address lines as select lines. When Enable=1, data passes to the selected output. This dual-use is why decoder and DEMUX ICs share part numbers (e.g. 74138).

Explanation: A 3-to-8 decoder generates all 8 minterms of 3 variables (A,B,C). So it can implement any 3-variable SOP function directly. For more variables you’d need a larger decoder.

Explanation: Step = V_REF / (2ⁿ−1) = 10000mV / 31 = 322.58mV. Wait — for R-2R, full-scale = V_REF×(2ⁿ−1)/2ⁿ = 10×31/32 = 9.6875V. Step = V_REF/2ⁿ = 10000/32 = 312.5 mV.

Explanation: A priority encoder always outputs the code for the highest-numbered active input. With D₄ and D₇ both HIGH, D₇ has higher priority → output = 7.

Explanation: True. The SAR ADC determines one bit per clock cycle, from MSB down to LSB. An 8-bit SAR always takes exactly 8 clock cycles regardless of the input value.

Explanation: A 16×4 PROM has 16 addresses (16 = 2⁴). The 4 address pins are connected to 4 input variables. Each of the 4 data output bits can implement one Boolean function of those 4 variables simultaneously.

Explanation: Step ≤ 1/100 → 2ⁿ ≥ 100 → 2⁷ = 128 ≥ 100. So 7 bits are sufficient (step = 1/128 ≈ 0.78% < 1%).

Explanation: CMOS has near-zero static power dissipation because in steady state one transistor of each complementary pair is always OFF, creating no DC current path from V_DD to GND.

Explanation: V_NH = VOH(min) − VIH(min) = 2.4V − 2.0V = 0.4V. Similarly V_NL = VIL(max) − VOL(max) = 0.8V − 0.4V = 0.4V. Both noise margins are equal at 0.4V for standard TTL.

Explanation: True. Saturated transistors store base charge that must be removed before switching. ECL keeps transistors in the active region using a differential amplifier with a reference voltage — eliminating storage time and achieving ~1ns propagation delay.

Explanation: The SBD (forward voltage ~0.25V) is placed between base and collector. When the transistor approaches saturation (V_CE → 0), the SBD conducts and clamps V_CE at ~0.4V — just above saturation — preventing charge storage and speeding up switching.

Explanation: The diode D in series with T₃’s emitter ensures T₃ cannot conduct when T₄ is fully ON (output LOW). Without D, both T₃ and T₄ would conduct simultaneously, creating a short-circuit current spike.

Explanation: False. Totem-pole outputs CANNOT be wired together — if one drives HIGH (T₃ ON) and another drives LOW (T₄ ON), a low-impedance path from V_CC to GND creates excessive current that damages the ICs. Open-collector outputs with a pull-up resistor are used for wired-AND.

Explanation: Fan-out = I_out(max) / I_in(per gate). The driver’s output can source/sink a limited current; each load draws/sinks a fixed input current. Exceeding fan-out causes the output voltage to drift out of the valid logic level range.

Explanation: In CMOS NAND: pull-down = NMOS in series (both inputs must be HIGH to pull output LOW), pull-up = PMOS in parallel (either input LOW keeps output HIGH). This is the fundamental CMOS gate topology rule.

Explanation: P = C·V²·f = 10×10⁻¹²× 25 × 100×10⁶ = 10⁻¹¹ × 2.5×10⁹ = 25×10⁻³ W = 25 mW.

Explanation: True. 74-series: 0°C to +70°C (commercial). 54-series: −55°C to +125°C (military grade). Electrical specifications are identical; the 54-series has tighter V_CC tolerance.

Explanation: True (for active-low enable). When ENABLE=LOW (active), the buffer drives normally. When ENABLE=HIGH, both output transistors are off — output floats (Hi-Z). This is how multiple devices share a common data bus.

Explanation: Speed-power product = t_pd × P = 10ns × 2mW = 10×10⁻⁹ × 2×10⁻³ = 20×10⁻¹² J = 20 pJ. Lower is better — 74LS is significantly better than standard TTL (100 pJ).

Explanation: S=R=1 forces both Q and Q̄ to 0 simultaneously — violating the complementary relationship. When inputs return to 0,0 the final state is unpredictable (critical race).

Explanation: Q(n+1) = J·Q̄ + K̄·Q. When J=K=0: Q(n+1)=Q (hold). J=1,K=0: Q(n+1)=1 (set). J=0,K=1: Q(n+1)=0 (reset). J=K=1: Q(n+1)=Q̄ (toggle).

Explanation: True. With J=K=1, the output toggles. But in a level-triggered implementation, the output toggles again immediately (since Q feeds back as the new input), creating an oscillation during the clock pulse width. Solved by edge-triggering or Master-Slave topology.

Explanation: Since Q(n+1) = D for a D-FF, and we want Q(n+1) = J·Q̄ + K̄·Q (JK characteristic), we connect D = J·Q̄ + K̄·Q. The Q feedback is wired from the D-FF’s Q output.

Explanation: Each clock pulse shifts in one bit. For a 4-bit register, exactly 4 clock pulses are needed to load all 4 bits, after which the full word is available simultaneously on Q₃Q₂Q₁Q₀.

Explanation: A Johnson counter with n flip-flops has 2n states. For n=4: 2×4=8 states. (Compare ring counter: n=4 → 4 states.)

Explanation: False. In an asynchronous (ripple) counter, only the first flip-flop receives the external clock. Each subsequent flip-flop is clocked by the Q output of the previous one — this is what causes the ripple delay and makes them asynchronous.

Explanation: Ripple delay = n × t_pd = 4 × 15 = 60 ns. The carry ripples through all 4 stages sequentially. This is why ripple counters limit maximum operating frequency.

Explanation: The general rule for synchronous binary UP counter: Tₙ = Q(n-1)·Q(n-2)·…·Q₀. For T₂ (bit 2): T₂ = Q₁·Q₀ — it toggles only when both lower bits are 1 (carry condition).

Explanation: The 74194 is the 4-bit bidirectional universal shift register. It supports 4 modes via S₁,S₀: no-change (00), shift-right (01), shift-left (10), parallel-load (11).

Explanation: True. When a multi-bit pointer crosses a clock domain, metastability can corrupt any bit. Binary counters change multiple bits at once (e.g. 0111→1000 changes 4 bits). If metastability strikes during this transition, the received value could be any random number. Gray code ensures only 1 bit changes — the worst case is reading the old or new value, never an invalid intermediate.

Explanation: With 5 flip-flops and no reset/skip logic, the counter cycles through all 2⁵ = 32 states. Modulus = 32.

Explanation: The weighted DAC needs resistors spanning a 2^(n-1) ratio — impossible to match precisely across temperature in silicon. R-2R needs only two values: their ratio (2:1) tracks each other accurately through PVT variations.

Explanation: Step = 10000mV / (2⁸−1) = 10000/255 ≈ 39.22 mV.

Explanation: EPROM uses UV light (25–30 minutes) to excite electrons off the floating gate, restoring all cells to logic 1. EEPROM improves this by using electrical erase (byte/word level, ~10ms) — no UV or quartz window needed.

Explanation: True. The 1T1C DRAM cell stores charge on a small capacitor (~10-30 fF). Leakage current discharges the capacitor in ~50-100ms. All rows must be refreshed within the specified refresh interval (typically 64ms for modern DRAM).

Explanation: 6T SRAM = 2 PMOS loads (Q3,Q4) + 2 NMOS drivers (Q1,Q2) forming cross-coupled inverters + 2 NMOS access transistors (Q5,Q6) controlled by the Word Line. Data held by the latch with no refresh needed.

Explanation: 16K = 16×1024 = 2¹⁴ locations. MAR must be able to address any of these 2¹⁴ locations → 14-bit MAR. The MBR = 8 bits (word length).

Explanation: PROM (Programmable ROM) uses fusible links that can be blown once by the user with a PROM programmer. Once a fuse is blown (bit set to 0), it cannot be restored — one-time programmable (OTP).

Explanation: True. When the word line is asserted, the capacitor shares charge with the bit line. The stored charge is partially transferred, reducing V_cap. The sense amplifier detects the small voltage difference and regenerates the cell — effectively rewriting it (restore after read).

Explanation: Total bits = 512K × 16 = 512×1024×16 = 8,388,608 bits = 8 Megabits (8 Mbit).

Explanation: RAS (Row Address Strobe) latches the 8-bit row address first, then CAS (Column Address Strobe) latches the 8-bit column address — together addressing 256×256=64K locations using only 8 address pins. This halves the pin count vs a direct 16-bit address.

Explanation: True. 4K = 4 × 1K. Four 1K×8 chips share the lower 10 address lines (A₉–A₀). A 2-to-4 decoder driven by A₁₁,A₁₀ (MSBs) selects exactly one chip’s CE at a time. All chips share the 8 data lines (parallel) for 8-bit words.

Explanation: Registers (~1 cycle / ps) → SRAM cache (5–50 ns) → DRAM (50–100 ns) → Flash (~100 μs read). This ordering matches the memory hierarchy pyramid — faster memories sit closer to the processor and are smaller and more expensive per bit.