In the fast-paced environment of PCI Express (PCIe), achieving reliable data transport is a monumental task. The PCIe specification demands an incredibly strict Bit Error Rate (BER) of no worse than 10−12, but transient electrical noise and interference are inevitable. Because a single flipped bit will corrupt an entire packet, the Data Link Layer utilizes a hardware-based mechanism to catch errors and guarantee perfect delivery.
At the heart of this error detection system are two crucial pieces of information appended to every outbound Transaction Layer Packet (TLP): a 32-bit Link Cyclic Redundancy Code (LCRC) and a unique incremental Sequence Number.
Here is how these two elements work together to ensure your data is received exactly as it was sent.
1. The 32-Bit LCRC (Catching Corrupted Bits)
Before a TLP leaves the transmitter, it passes through the LCRC Generator. This logic block evaluates all the fields of the outgoing packet—including the Sequence Number, Header, Data Payload, and optional ECRC—and calculates a 32-bit check code that is attached to the end of the packet.
While the LCRC does not automatically correct errors the way ECC memory does, it provides incredibly robust error detection. It is particularly highly effective at catching “burst errors”—strings of incorrect bits that are common in high-speed serial links.
When the TLP reaches the receiving device, the first thing the receiver does is calculate its own LCRC based on the received bits. It then compares its calculated LCRC to the 32-bit LCRC attached to the packet. If they do not match perfectly, a bit error occurred in transit. The receiver immediately drops the corrupted packet and prepares to send a “Nak” to ask the transmitter to replay it.
2. Incremental Sequence Numbers (Catching Lost Packets)
Error detection isn’t just about spotting corrupted bits; it is also about ensuring no packets simply disappear en route. To manage this, the transmitter uses a 12-bit counter called NEXT_TRANSMIT_SEQ.
Before the LCRC is calculated, this counter assigns a unique, incremental Sequence Number to every outbound TLP. The counter starts at 0, counts forward with every packet sent up to a maximum of 4095, and then rolls over back to 0 to keep counting.
This numbering system is critical because the golden rule of the PCIe Data Link Layer is that TLPs must be successfully received in the exact order they were sent.
3. The Receiver’s Sequence Verification
To enforce this golden rule, the receiving device maintains its own 12-bit counter called NEXT_RCV_SEQ, which tracks the exact Sequence Number it expects to see next.
If an incoming TLP passes the LCRC check perfectly, the receiver then evaluates its Sequence Number. There are three possible outcomes:
- A Perfect Match: If the incoming Sequence Number matches the
NEXT_RCV_SEQcount, everything is working perfectly. The TLP is accepted and forwarded to the Transaction Layer, and the expected sequence counter increments by one to wait for the next packet. - An Earlier Number (A Duplicate): If the incoming number is earlier than expected, the receiver knows it is a duplicate packet it has already processed. This is not an error; it simply drops the harmless duplicate and reminds the transmitter of its furthest progress by sending an Ack with the last good sequence number.
- A Later Number (A Lost Packet): If the incoming number is later than expected (for example, expecting packet 30 but receiving packet 31), the receiver immediately knows a packet was lost or dropped earlier. Because TLPs must be processed in order, it discards this out-of-sequence packet and sends a Nak to force the transmitter to replay the missing sequence.
Summary The Data Link Layer leaves nothing to chance. By utilizing a 32-bit LCRC to aggressively sniff out transient bit errors and 12-bit Sequence Numbers to enforce strict in-order delivery, PCIe ensures that missing or corrupted packets are instantly identified and recovered.