In a high-speed PCI Express (PCIe) architecture, a device is constantly juggling multiple types of outbound traffic. At any given moment, the transmitter might have brand-new data arriving from the Transaction Layer, crucial Ack or Nak messages generated by the Data Link Layer, or low-level Link training messages required by the Physical Layer.
Because all of this traffic must share a single physical connection, the hardware needs a strict set of rules to determine exactly what goes onto the wire next. To manage this traffic jam, the PCIe specification recommends a very specific packet scheduling hierarchy.
Here is a look at how PCIe devices prioritize packets, ensuring that critical link maintenance and error recovery always take precedence over new data.
The Golden Rule: Never Interrupt
Before we look at the queue, we have to establish the absolute highest priority in PCIe scheduling: the completion of any Transaction Layer Packet (TLP) or Data Link Layer Packet (DLLP) currently in progress.
Once a packet begins transmission, it cannot be interrupted or preempted. Even if a highly critical error occurs and the receiver immediately schedules a “Nak” distress signal, the hardware is required to delay the transmission of that Nak until the current outgoing packet has completely finished crossing the link.
The Priority Hierarchy
Once the physical wire is free, the device consults a strict, 8-step recommended priority list to select the next packet for transmission:
- Completion of current packet: As noted above, finishing what is already in progress is the highest priority.
- Ordered Sets: These are specialized, low-level Physical Layer messages used for vital link training and recovery. Because the link cannot function at all without physical stability, these beat all standard packets.
- Nak (Negative Acknowledge): Error reporting is highly urgent. If a corrupted packet is detected, halting the pipeline and demanding a replay via a Nak takes precedence over standard confirmations.
- Ack (Acknowledge): Confirming successful packet delivery is the next highest priority, as sending Acks allows the neighboring device to safely purge its Replay Buffer and keep the data pipeline moving.
- Flow Control: Transmitting flow control credits ensures the neighboring device knows it has the necessary buffer space to send its own data, preventing buffer overflows.
- Replay Buffer re-transmissions: Rescuing lost or corrupted data takes precedence over sending completely new data.
- Waiting TLPs from the Transaction Layer: Standard, brand-new data packets from the software layer are actually quite low on the list. They must wait until all link health and error-recovery mechanisms are fully satisfied.
- All other DLLP transmissions: Any remaining localized link traffic (such as power management requests) falls to the very bottom of the queue, representing the lowest priority.
Summary The PCIe packet scheduling hierarchy is a perfect reflection of the architecture’s design philosophy: stability and reliable transport come before raw throughput. By strictly prioritizing physical link health (Ordered Sets) and immediate error recovery (Naks, Acks, and Replays) over the introduction of new Transaction Layer Packets, the system ensures that the data pipeline remains perfectly ordered, highly reliable, and resistant to catastrophic failure.