In the PCI Express (PCIe) Data Link Layer, the timers that manage the Ack/Nak protocol—specifically the AckNak_LATENCY_TIMER and the REPLAY_TIMER—are not arbitrary countdowns. Their timeout limits are dynamically calculated using precise mathematical formulas that adapt to the physical capabilities of the link.
As PCIe architecture evolved from Generation 1 to Generation 3, the speed at which data travels across the wire increased dramatically. To maintain reliable transport without suffocating the link’s bandwidth, the math behind these timers had to scale accordingly.
Here is a deep dive into the formulas that configure these crucial watchdogs and how their baseline metrics shift across PCIe generations.
The Foundation: Symbol Times
The resulting timeout values calculated for both the AckNak_LATENCY_TIMER and the REPLAY_TIMER are expressed in “symbol times”,. A symbol time is simply the amount of time it takes to transmit one single symbol across the physical link.
Because link speeds increase with each generation, the duration of a symbol time shrinks accordingly:
- Gen1 (2.5 GT/s): One symbol time is exactly 4ns,.
- Gen2 (5.0 GT/s): The time is halved, making one symbol time 2ns,.
- Gen3 (8.0 GT/s): Because Gen3 drops the older 8b/10b encoding in favor of 128b/130b encoding, the measurement shifts. The symbol time is 1ns, or specifically calculated as 1.25ns to transmit 1 byte,.
The Mathematical Formulas
To determine how many symbol times a device must wait before an event triggers, the PCIe specification dictates two primary formulas:
1. The AckNak_LATENCY_TIMER Equation This timer dictates how long a receiver can wait before it must send an acknowledgement. The formula is: ( (Max_Payload_Size + TLPOverhead) * AckFactor ) / LinkWidth + InternalDelay + Tx_L0s_Adjustment.
2. The REPLAY_TIMER Equation This timer serves as the transmitter’s watchdog. Because the transmitter must allow enough time for a packet to reach the receiver, be processed, and for an Ack to be returned, the REPLAY_TIMER is mathematically engineered to be exactly three times longer than the AckNak_LATENCY_TIMER. The formula is: ( (Max_Payload_Size + TLPOverhead) * AckFactor ) / LinkWidth * 3 + InternalDelay * 3 + Rx_L0s_Adjustment.
Breaking Down the Variables
Both formulas share a core set of variables that allow the timers to perfectly match the specific hardware configuration of the link:
- Max_Payload_Size: The maximum allowable data payload size, pulled from the device’s Device Control Register,.
- TLPOverhead: The extra size added to the packet by non-data fields (such as the Sequence Number, Header, Digest, LCRC, and framing symbols). The formula treats this as a constant of 28 symbols,.
- AckFactor (AF): A designated “fudge factor” ranging from 1.0 to 3.0,. It represents the number of maximum payload-sized TLPs that can be received before an Ack is mandatory,. Hardware engineers tweak this variable to balance Link bandwidth efficiency against the physical size of the Replay Buffer,.
- LinkWidth: The number of active lanes, ranging from x1 up to x32,.
- InternalDelay: This accounts for the internal processing time required for the receiver to process a TLP and the transmitter to process an Ack,. This value scales up dramatically across generations: it is defined as 19 symbol times for Gen1, 70 for Gen2, and 115 for Gen3,.
The Evolution of the L0s Adjustment
If you look closely at the formulas above, you will notice the variables Tx_L0s_Adjustment and Rx_L0s_Adjustment. These were originally included in the 1.x (Gen1) PCIe specifications to account for the extra latency caused by the Link waking up from the L0s low-power state,.
Interestingly, when the spec writers created their default timeout tables for Gen1, they actually assumed these L0s recovery values were zero, resulting in “unadjusted” timer values,,.
Beginning with the 2.0 (Gen2) PCIe specification, the L0s adjustment variables were dropped from the equations entirely. For Gen2 and Gen3, the text simply states that if a transmitter utilizes the L0s power state, it must independently compensate for the exit latency—either by statically adding extra time to the table values or dynamically sensing the power state and allowing extra leeway.
Summary PCIe timers are highly dynamic, adjusting themselves based on lane width, payload sizes, and internal hardware delays. By anchoring these mathematical formulas to “symbol times,” the PCIe specification elegantly ensures that as newer generations push data faster (scaling from 4ns down to 1ns per symbol), the system’s error-recovery watchdogs naturally scale alongside them.