In our ongoing exploration of the PCIe Data Link Layer, we have seen how Data Link Layer Packets (DLLPs) act as localized messengers to manage flow control and verify data integrity. However, these specialized packets have another critical responsibility: handling link power management.
When a system needs to conserve energy, connected devices cannot simply shut down their connections unannounced. Instead, their Data Link Layers use specialized Power Management DLLPs to coordinate and negotiate transitions into lower-power states.
Here is a breakdown of the specific DLLPs used to manage link power and the physical format they take on the wire.
The Four Power Management DLLPs
The PCIe specification defines a specific group of DLLPs dedicated to power management. When a device needs to change its power state, it sends one of these packets to its direct neighbor. The receiving device determines the DLLP’s purpose by looking at its 1-byte “Type” field.
The sources outline four specific Power Management DLLP variants:
- PM_Enter_L1 (Type: 0010 0000b): This packet is sent to request that the link transition into the L1 power conservation state.
- PM_Enter_L23 (Type: 0010 0001b): This packet requests that the link drop into the even deeper L2 or L3 power management states.
- PM_Active_State_Request_L1 (Type: 0010 0011b): This packet is used to negotiate entry specifically into the L1 Active State Power Management (ASPM) condition.
- PM_Request_Ack (Type: 0010 0100b): Because devices must agree to power state transitions, this packet is used by the receiving device to safely acknowledge the power management requests listed above.
The Format of a Power Management DLLP
Like all Data Link Layer Packets, Power Management DLLPs are strictly “local traffic” that carry no routing information and are fixed at exactly 8 bytes in length. Because they simply trigger state transitions, their physical anatomy is incredibly straightforward:
1. The Type Field (Byte 0) The first byte of the packet contains the 8-bit binary code (such as 0010 0000b) that identifies exactly which of the four power management messages is being transmitted.
2. Reserved Space (Bytes 1, 2, and 3) Unlike Flow Control DLLPs that require extra bytes to communicate available buffer credits, Power Management requests are simple triggers. Because no extra attributes are needed, the remaining three bytes of the 4-byte DLLP core are simply marked as “Reserved”.
3. The 16-bit CRC (Bytes 4 and 5) To guarantee that the power management request wasn’t corrupted by a transient bit error while crossing the link, a 16-bit Cyclic Redundancy Check (CRC) is calculated and appended to the core. This CRC calculation is based on all four bytes of the core (Bytes 0-3), regardless of whether those reserved fields are actively used.
4. Framing Boundaries Before the packet is passed to the physical wire, it is padded out to its final 8-byte footprint using standard framing symbols. Depending on the PCIe generation, this means adding a Start of DLLP (SDP) and End Good (END) symbol for 8b/10b encoding, or an SDP token for Gen3’s 128b/130b encoding.
Summary
Power Management DLLPs are the quiet negotiators of the PCIe link. By utilizing a lightweight, un-routed 8-byte packet structure to request and acknowledge low-power states, the Data Link Layer ensures that devices can seamlessly transition into energy-saving modes without disrupting the integrity of the broader system.