// ============================================================
// Testbench  : rca_4bit_tb
// DUT        : rca_4bit  (structural, half-adder based)
// Reference  : rca_4bit_behavioral  (arithmetic model)
// Strategy   : Corner cases + pseudo-random stimulus
//              Dual-instantiation comparison methodology
// ============================================================
`timescale 1ns/1ps
`default_nettype none

module rca_4bit_tb;

  // ── Shared stimulus ────────────────────────────────────────
  reg  [3:0] a, b;
  reg         cin;

  // ── DUT outputs ───────────────────────────────────────────
  wire [3:0] dut_sum;
  wire        dut_cout;

  // ── Reference model outputs ────────────────────────────────
  wire [3:0] ref_sum;
  wire        ref_cout;

  // ── Instantiate DUT (structural half-adder based) ──────────
  rca_4bit dut (
    .a   (a       ),
    .b   (b       ),
    .cin (cin     ),
    .sum (dut_sum ),
    .cout(dut_cout)
  );

  // ── Instantiate reference model ────────────────────────────
  rca_4bit_behavioral ref_model (
    .a   (a       ),
    .b   (b       ),
    .cin (cin     ),
    .sum (ref_sum ),
    .cout(ref_cout)
  );

  // ── Waveform dump ──────────────────────────────────────────
  initial begin
    $dumpfile("rca_4bit.vcd");
    $dumpvars(0, rca_4bit_tb);
  end

  // ── Test tracking ──────────────────────────────────────────
  integer pass_cnt = 0, fail_cnt = 0, test_num = 0;
  integer seed     = 42;

  // ── Self-checking task ─────────────────────────────────────
  task check;
    input [3:0] ta, tb;
    input        tc;
    begin
      a = ta; b = tb; cin = tc;
      #5;   // propagation settling
      test_num++;

      if (dut_sum  === ref_sum  &&
          dut_cout === ref_cout) begin
        $display("  PASS [%3d]  %04b + %04b + %b = %b_%04b  (%0d+%0d+%b=%0d)",
          test_num, a, b, cin, dut_cout, dut_sum,
          a, b, cin, {dut_cout,dut_sum});
        pass_cnt++;
      end else begin
        $display("  FAIL [%3d]  a=%04b b=%04b cin=%b | DUT=%b_%04b REF=%b_%04b",
          test_num, a, b, cin,
          dut_cout, dut_sum, ref_cout, ref_sum);
        fail_cnt++;
      end
      #5;
    end
  endtask

  // ── Main test program ──────────────────────────────────────
  initial begin
    $display("\n================================================================");
    $display("  4-bit RCA Testbench — DUT vs Behavioral Reference Model");
    $display("================================================================");

    a=0; b=0; cin=0; #10;

    // ── Section 1: Corner Cases ────────────────────────────────
    $display("\n  --- CORNER CASES ---");
    check(4'h0, 4'h0, 0);   // 0+0+0 = 0
    check(4'h0, 4'h0, 1);   // 0+0+1 = 1
    check(4'hF, 4'h0, 0);   // 15+0  = 15
    check(4'h0, 4'hF, 0);   // 0+15  = 15
    check(4'h1, 4'h1, 0);   // 1+1   = 2
    check(4'h5, 4'h5, 0);   // 5+5   = 10
    check(4'hA, 4'h5, 0);   // 10+5  = 15

    // ── Section 2: Overflow Cases (cout=1 expected) ────────────
    $display("\n  --- OVERFLOW CASES (expect cout=1) ---");
    check(4'hF, 4'h1, 0);   // 15+1  = 16 (overflow!)
    check(4'hF, 4'hF, 0);   // 15+15 = 30 (overflow!)
    check(4'hF, 4'hF, 1);   // 15+15+1=31 (max possible)
    check(4'h8, 4'h8, 0);   // 8+8   = 16 (overflow)
    check(4'hA, 4'hA, 0);   // 10+10 = 20 (overflow)
    check(4'hE, 4'h3, 0);   // 14+3  = 17 (overflow)

    // ── Section 3: Carry-in variations ────────────────────────
    $display("\n  --- CARRY-IN VARIATIONS ---");
    check(4'h7, 4'h7, 0);   // 7+7   = 14
    check(4'h7, 4'h7, 1);   // 7+7+1 = 15
    check(4'h7, 4'h8, 0);   // 7+8   = 15
    check(4'h7, 4'h8, 1);   // 7+8+1 = 16 (overflow)
    check(4'hE, 4'h1, 0);   // 14+1  = 15
    check(4'hE, 4'h1, 1);   // 14+1+1= 16 (overflow)

    // ── Section 4: Identity patterns ──────────────────────────
    $display("\n  --- IDENTITY PATTERNS ---");
    check(4'h0, 4'h0, 0);   // additive identity
    check(4'h5, 4'h0, 0);   // a + 0 = a
    check(4'h0, 4'h9, 0);   // 0 + b = b
    check(4'h3, 4'h3, 0);   // a + a = 2a (no overflow)
    check(4'h6, 4'h6, 0);   // a + a = 2a (no overflow)

    // ── Section 5: Pseudo-random sweep ────────────────────────
    $display("\n  --- PSEUDO-RANDOM VECTORS (32 vectors) ---");
    begin : random_loop
      integer i;
      for (i=0; i<32; i=i+1) begin
        check(
          {$random(seed)} % 16,   // random a: 0..15
          {$random(seed)} % 16,   // random b: 0..15
          {$random(seed)} % 2     // random cin: 0 or 1
        );
      end
    end

    // ── Final summary ──────────────────────────────────────────
    $display("\n================================================================");
    $display("  RESULTS: %0d / %0d PASS  |  %0d FAIL",
             pass_cnt, test_num, fail_cnt);
    $display("================================================================");

    if (fail_cnt == 0)
      $display("  ✅ ALL TESTS PASSED — 4-bit RCA verified correct\n");
    else
      $fatal(1, "  ❌ %0d TEST(S) FAILED\n", fail_cnt);

    #20; $finish;
  end

  // ── Continuous monitor ─────────────────────────────────────
  initial
    $monitor("  @%0t  a=%0d b=%0d cin=%b → sum=%0d cout=%b",
             $time, a, b, cin, dut_sum, dut_cout);

endmodule

`default_nettype wire