// Behavioral
always @(*) y = ~a;

// Data Flow
assign y = ~a;

// Gate Level
not g1(y, a);

// Switch Level — explicit transistors
pmos p1(y, vdd, a);   // pull-up: ON when a=0
nmos n1(y, gnd, a);   // pull-dn: ON when a=1

// Syntax: nmos instance_name(drain, source, gate);
nmos n1(drain, source, gate);

// Example: pull-down in a CMOS inverter
supply0 GND;
nmos n_inv(out, GND, in);  // when in=1 → out pulled to GND (0)

// Multiple nmos in series (stacked pull-down)
wire mid;
nmos na(out,  mid, a);   // both must be ON to pull out low
nmos nb(mid,  GND, b);   // implements NAND pull-down network

// Syntax: pmos instance_name(drain, source, gate);
pmos p1(drain, source, gate);

// Example: pull-up in a CMOS inverter
supply1 VDD;
pmos p_inv(out, VDD, in);  // when in=0 → out pulled to VDD (1)

// Multiple pmos in parallel (pull-up network for NAND)
pmos pa(out, VDD, a);    // either one pulls out high
pmos pb(out, VDD, b);    // if a=0 OR b=0, out=1 (NAND pull-up)

// rnmos: models a resistive pass transistor
// Common in dynamic logic and pass-gate networks
rnmos rn1(out, in, enable);

// Resistive pull-up using rpmos
supply1 VDD;
rpmos   rp1(net, VDD, 1'b0); // always-on weak pull-up (gate tied low)
// net has a weak pull-up — any strong driver overrides it

// Practical use: pseudo-NMOS inverter
// rpmos acts as a weak pull-up load
rpmos load(out, VDD, 1'b0);  // weak1 pull-up
nmos  pull(out, GND, in);   // strong0 pull-down when in=1
// When in=1: strong0 from nmos beats weak1 from rpmos → out=0
// When in=0: nmos OFF, rpmos drives weak1 → out=1 (weak)

// cmos primitive: 4 ports — (out, data, nctrl, pctrl)
cmos tg1(out, data, nctrl, pctrl);

// Equivalent using separate nmos + pmos:
nmos n1(out, data, nctrl);
pmos p1(out, data, pctrl);

// Resistive version
rcmos rtg1(out, data, nctrl, pctrl);

// 2-to-1 MUX using two CMOS transmission gates
wire sel_n;
not g_inv(sel_n, sel);
cmos tg_a(out, a, sel,   sel_n); // a passes when sel=1
cmos tg_b(out, b, sel_n, sel);  // b passes when sel=0

module inv_switch (
  input  in,
  output out
);
  supply1 VDD;
  supply0 GND;

  pmos p1(out, VDD, in);  // pull-up:  ON when in=0 → out=1
  nmos n1(out, GND, in);  // pull-dn: ON when in=1 → out=0
endmodule

module nand2_switch (
  input  a, b,
  output y
);
  supply1 VDD;
  supply0 GND;
  wire    mid;

  // Pull-up network (PUN) — PMOS in PARALLEL
  // If a=0 OR b=0 → at least one PMOS ON → y=1
  pmos pa(y,   VDD, a);  // ON when a=0
  pmos pb(y,   VDD, b);  // ON when b=0

  // Pull-down network (PDN) — NMOS in SERIES
  // Only if a=1 AND b=1 → both ON → y=0
  nmos na(y,   mid, a);  // ON when a=1
  nmos nb(mid, GND, b);  // ON when b=1
endmodule

module nor2_switch (
  input  a, b,
  output y
);
  supply1 VDD;
  supply0 GND;
  wire    mid;

  // Pull-up network (PUN) — PMOS in SERIES
  // Only if a=0 AND b=0 → both ON → y=1
  pmos pa(mid, VDD, a);  // ON when a=0
  pmos pb(y,   mid, b);  // ON when b=0

  // Pull-down network (PDN) — NMOS in PARALLEL
  // If a=1 OR b=1 → at least one ON → y=0
  nmos na(y, GND, a);    // ON when a=1
  nmos nb(y, GND, b);    // ON when b=1
endmodule

module sram_6t (
  inout  bl, blb,    // bit line and bit line bar (complementary)
  input  wl         // word line (row select)
);
  supply1 VDD;
  supply0 GND;
  wire    q, qn;    // internal storage nodes

  // Cross-coupled inverter pair (storage element)
  pmos p1(q,  VDD, qn);  nmos n1(q,  GND, qn);  // INV1: qn→q
  pmos p2(qn, VDD, q);   nmos n2(qn, GND, q);   // INV2: q→qn

  // Access transistors (controlled by word line)
  // tranif1: bidirectional — enables read AND write on same path
  tranif1 t1(q,  bl,  wl);  // q  ↔ bl  when wl=1
  tranif1 t2(qn, blb, wl);  // qn ↔ blb when wl=1
endmodule

module bidir_pad (
  inout  pad,          // connects to external pin
  input  data_out,     // data to drive onto pad
  output data_in,      // data read from pad
  input  oe            // output enable: 1=drive, 0=receive
);
  // Output path: drive pad when oe=1
  tranif1 tx(pad, data_out, oe);   // pad ↔ data_out when oe=1

  // Input path: always read from pad
  tran    rx(data_in, pad);       // data_in always connected to pad

  // When oe=0: tranif1 disconnected → pad floats to external signal
  // When oe=1: tranif1 drives pad with data_out
endmodule

module dynamic_and (
  input  clk, a, b,
  output out
);
  supply1 VDD;
  supply0 GND;
  wire    clkn, mid;

  not inv_clk(clkn, clk);

  // Precharge: when clk=0 (clkn=1), pmos charges out to VDD
  pmos    pre(out, VDD, clk);    // ON when clk=0

  // Evaluate: when clk=1, nmos PDN can discharge out
  nmos    na(out, mid, a);      // stack: a AND b pull out low
  nmos    nb(mid, GND, b);

  // Keeper: weak pmos holds precharged value if a or b = 0
  rpmos   keep(out, VDD, clkn); // weak pull-up during evaluate
endmodule

// I2C SDA line: open-drain topology
// Multiple devices drive low; external resistor pulls high
module i2c_bus_sw (
  inout sda,
  input drv_a, drv_b   // 0 = device wants to pull low
);
  // External pull-up resistor (modelled by pullup)
  pullup r_ext(sda);          // pull1 strength — weak

  // Open-drain drivers: nmos pulls low, no pull-high inside device
  nmos dev_a(sda, 1'b0, !drv_a); // drv_a=0 → nmos ON → sda=0
  nmos dev_b(sda, 1'b0, !drv_b); // drv_b=0 → nmos ON → sda=0

  // Result: sda = 0 if any device drives; 1 (weak) otherwise
  // → open-drain wired-AND behaviour
endmodule