PCIe Series — Complete Index — VLSI Trainers

VLSI Trainers · PCIe Series

Complete PCIe Series Index

Every post in the series, in order. Click any card to go directly to that article.

30+Posts Planned

6Phases

Gen 1–6Coverage

0Spec Reading Required

Welcome to the PCIe Series 👋

What the series covers, who it’s for, and how to get the most out of it — read this first.

Phase 1 Foundations

Introduction to PCIe

Why PCIe replaced PCI, key design goals, scalability, and the point-to-point topology

PCIe Architecture — Topology and Components

Root complex, switch, endpoint, bridge — roles, hierarchy, and how they connect

The Three-Layer Model

Transaction, Data Link, and Physical layers — what each does and how they interact

PCIe Generations — Gen 1 to Gen 6

Speed, encoding changes, bandwidth per lane, and what changed in each generation

Phase 2 Transaction Layer

TLP Structure — Common Header Fields

TLP format, type, length, TC, AT, EP, TD, ECRC — every common header field explained

Memory Read and Write TLPs

MRd, MWr, MRdLk — 32-bit and 64-bit addressing, byte enables, and payload rules

Completion TLPs

Cpl, CplD, CplLk — requester ID, tag, byte count, lower address, and split-completion

Configuration TLPs

CfgRd0, CfgRd1, CfgWr0, CfgWr1 — type 0 vs type 1, bus/device/function addressing

Msg and MsgD — INTx, PME, error signalling, slot power, vendor-defined messages

TLP Ordering Rules

The 12-rule ordering table — posted vs non-posted vs completion, and why order matters

Address Translation — AT Field, ATS, and PRI

Address type field, Address Translation Services, and Page Request Interface for IOMMU

Phase 3 Data Link Layer

Data Link Layer — DLLPs and Reliability

DLLP types, sequence numbers, retry buffer, ACK/NAK protocol, and replay mechanism

Credit types (PH, PD, NPH, NPD, CPLH, CPLD), credit initialisation, and credit return

Phase 4 Physical Layer

Physical Layer — Lanes, Differential Signalling & Electrical

What a lane is, differential pairs, impedance, voltage swing, and common mode

8b/10b Encoding

Why encoding is needed, how 8b/10b works, disparity, special symbols, and overhead

128b/130b Encoding (Gen 3+)

Why 8b/10b was replaced, how 128b/130b works, sync headers, and scrambling

Link Training and LTSSM

All 11 LTSSM states, substates, detect → polling → configuration → L0 walkthrough

Phase 5 Configuration Space & Power Management

Configuration Space — Type 0 Header

Vendor/Device ID, Command, Status, Class Code, BARs, Subsystem, Capabilities Pointer

Configuration Space — Type 1 Header (Bridge)

Primary/secondary/subordinate bus numbers, I/O base/limit, memory base/limit, bridge control

Base Address Registers (BARs)

Memory vs I/O BARs, 32 vs 64-bit, prefetchable, sizing algorithm, and ROM BAR

Capability Structures

Linked list of capabilities, PCIe capability, MSI, MSI-X, power management capability

Extended Configuration Space

4KB extended space, AER, VCID, PASID, LTR, L1 Sub-States — what lives beyond 256 bytes

PCIe Enumeration

How the OS discovers devices, assigns bus numbers, allocates BARs, and enables the hierarchy

Interrupts — INTx, MSI, and MSI-X

Legacy pin interrupts vs MSI message writes vs MSI-X table — how each works and when to use which

Power Management — ASPM and Link States

L0, L0s, L1, L1.1, L1.2, L2/L3 — entry/exit latency, hardware vs software control, ASPM policy

Device Power States — D0 to D3

D0 active, D1, D2, D3hot, D3cold — context retention, PME, and wake signalling

Phase 6 Advanced Topics

Advanced Error Reporting (AER)

Correctable vs uncorrectable errors, error masks, ECRC, error forwarding, and AER capability

SR-IOV — Single Root I/O Virtualisation

Physical functions, virtual functions, VF BARs, VF enumeration, and use in virtualised servers

Device-initiated DMA, IOMMU address translation, DMA remapping tables, and security implications

PCIe 5.0, 6.0 — PAM4, FEC and What Changed

32 GT/s PAM4 signalling, forward error correction, flit-based framing in Gen 6, and bandwidth trajectory

Series Complete

You Made It — A Look Back at Everything 🎉

A recap of every major concept and skill you built across the full PCIe series.