A look back at every major concept, mechanism, and skill built across the full 30-post PCIe series — from the first differential pair to 64 GT/s PAM4, from a Vendor ID probe to SR-IOV VF assignment, from 8b/10b to Reed-Solomon FEC and flit mode.
PCIe is not one thing — it is a complete system. It is the physical pair of differential wires carrying a 64 GT/s PAM4 signal. It is the 128-bit header describing a memory write transaction. It is the depth-first scan algorithm that discovers every device at boot. It is the IOMMU page table that enforces DMA isolation between virtual machines. It is the SR-IOV VF assigned to a VM’s NIC in a cloud data centre. All of it connects.
This wrap-up page catalogues every post in the series, maps which concepts connect to which, and lists the practical skills you built along the way. Use it as a reference when something comes up in hardware bring-up, driver debugging, or system design — the answer is almost certainly in one of these posts.
PCIe is layered, but the layers are not independent — every layer depends on mechanisms in the layers below it, and every system feature connects to both hardware and software.
Completing the series means you can do all of the following from first principles — without looking up basic definitions:
The series covered PCIe from the spec perspective. The natural next areas to explore — all of which build directly on what you learned here:
drivers/pci/ in the kernel implements everything in PCIe-23 (pci_scan_bus, pci_assign_resource), PCIe-24 (pci_enable_msi_range, pci_alloc_irq_vectors), PCIe-26 (pci_set_power_state), and PCIe-29 (dma_alloc_coherent, iommu_map).