PCIe Power Management Explained — ASPM and Link States

⚡ Power Management Overview

PCIe defines two complementary power management systems. Device Power Management (D-states, covered in PCIe-21) controls the function’s internal logic — register state, clocks, and device-specific power rails. Link Power Management (L-states, this post) controls the PCIe link itself — whether the transmitters are actively sending symbols, whether the reference clock is present, and whether PLLs are running.

The two systems are tightly coupled: placing a device in D1/D2/D3hot automatically triggers an L1 transition on its link. Link power management can also operate autonomously through ASPM (Active State Power Management) — hardware-controlled transitions that happen without any software involvement, purely based on link activity.

Understanding all L-states is essential for both hardware designers and driver writers. Incorrect ASPM configuration is one of the most common causes of system instability and unexpected wake latency.

📋 Link State Map

Figure 1 — PCIe link power states. Left to right: more power savings, more exit latency. L0p is unique to Gen 6 PAM4 links. L0, L0s, L1 and its sub-states, and L0p are all hardware-autonomous via ASPM. L2 and L3 require an OS-initiated power-down sequence.

📋 L0 — Normal Operation

L0 is the fully operational link state. All lanes are transmitting symbols continuously — either data (TLPs and DLLPs) or idle symbols when there is nothing to send. The PLL is locked, the reference clock is running, both transmitters and receivers are fully active, and the Data Link Layer reports DL_Active. All PCIe traffic flows only in L0.

There is no entry latency to L0 — when the link is already in L0 and a device needs to send, it sends immediately. Exit from L0 is initiated by either side entering electrical idle (signaling L0s entry) or by a negotiated sequence (L1 entry). The LTSSM is in the L0 state.

📋 L0s — One-Direction Standby

L0s is a fast standby state where one direction of the link enters electrical idle while the other direction can remain active. Each direction of a link operates its LTSSM independently — the transmitter of one side can be in L0s.Idle while its receiver is still in L0, ready to accept data. This asymmetry is intentional and avoids synchronisation overhead.

L0s is the lightest ASPM state. It provides power savings by stopping the transmitter’s signal transitions (which are a significant power consumer at high data rates) without requiring negotiation with the link partner. Entry is local to one transmitter — no DLLPs are exchanged to initiate it.

Figure 2 — L0s asymmetry. Each direction has its own LTSSM. Device A’s transmitter is in L0s (electrical idle, no signal transitions) while Device B’s transmitter is still in L0, sending data upstream. Device A’s receiver stays in L0, ready to receive Device B’s packets. Both devices can independently decide when to enter L0s on their transmit side.

▶ L0s Entry and Exit

Entering L0s

When a transmitter decides to enter L0s (typically due to an inactivity timeout — no TLPs or DLLPs queued), it:

Sends one EIOS (Electrical Idle Ordered Set) — for Gen 1/2, this is four 8b/10b special characters; for Gen 3+, it is a full block of 66h bytes.
Enters electrical idle within 8ns of sending the last EIOS symbol.
Remains in the Tx_L0s.Idle substate with the link in electrical idle.

The link partner’s receiver sees the EIOS and transitions to Rx_L0s — it arms its electrical-idle-exit detector and awaits the exit sequence.

Exiting L0s

When the transmitter needs to send again, it exits L0s using Fast Training Sequences (FTS). FTS ordered sets are specifically designed for rapid clock recovery after electrical idle — they provide dense transitions at a fixed known pattern so the receiver’s CDR (Clock and Data Recovery) circuit can quickly regain bit lock and symbol lock.

Transmitter sends N_FTS FTS ordered sets (count previously negotiated in TS2s during Configuration.Complete).
Transmitter follows FTS with one SOS (Skip Ordered Set) for 8b/10b encoding, or one EIEOS+SDS for 128b/130b encoding.
Receiver achieves bit lock and symbol/block lock during the FTS sequence.
Both sides return to L0 state — ready for TLPs and DLLPs.

N_FTS determines L0s exit latency. N_FTS is the number of Fast Training Sequences that the receiver needs to re-establish clock synchronisation. Devices report this value in TS2 ordered sets during link training (Configuration.Complete substate). If the link uses a common reference clock (Common Clock Configuration bit set), shorter FTS sequences are needed — which is why Common Clock Configuration reduces L0s exit latency. After updating Common Clock Configuration, software must set Retrain Link to re-negotiate N_FTS.

L0s exit latency (Link Capability [14:12])	Encoding	Typical range
Less than 64 ns	000b	N_FTS × 4 ns at 2.5 GT/s
64 ns to less than 128 ns	001b	Common clock config: often 001b
128 ns to less than 256 ns	010b	Spread-spectrum clocking: 010b–011b
256 ns to less than 512 ns	011b	—
512 ns to less than 1 µs	100b	—
1 µs to less than 2 µs	101b	—
2 µs to 4 µs	110b	—
More than 4 µs	111b	Unusual — independent clock source

📋 L1 — Bilateral Electrical Idle

L1 is a deeper power state than L0s. Both directions of the link enter electrical idle simultaneously — both transmitters stop signalling. The main power supply, reference clock, and PLLs all remain active in standard L1, distinguishing it from L1.1 and L1.2 where these are progressively removed.

L1 provides significantly more power savings than L0s because both PHY transceivers are idle, but it costs significantly more to exit — both directions must go through the Recovery LTSSM state (TS1/TS2 exchange) before reaching L0 again, whereas L0s only needs FTS sequences.

L1 can be entered two ways:

ASPM L1 — hardware-autonomous. The downstream port (endpoint or switch upstream port) decides to request L1 after the link has been idle. A DLLP negotiation takes place before entry.
Software-initiated L1 — when software places the device in D1, D2, or D3hot, the device automatically requests L1 on its link.

▶ L1 Entry Handshake

Unlike L0s, L1 requires negotiation because both directions must enter electrical idle together. A race condition without negotiation could leave one side in L0 sending TLPs while the other side has already powered down:

Figure 3 — L1 ASPM entry handshake. Step ①: Downstream blocks TLPs, waits for replay buffer empty, ensures FC credits sufficient for largest possible TLP on exit. Step ②: Repeatedly sends PM_Active_State_Request_L1 DLLP. Step ③: Upstream similarly prepares. Step ④: Upstream sends PM_Request_ACK repeatedly. Step ⑤: Downstream stops, sends EIOS, enters EI. Step ⑥: Upstream detects EI, sends its EIOS, enters EI. Both transmitters now silent — L1 achieved.

The upstream port can reject the L1 request by sending PM_Active_State_NAK — a Message TLP (not a DLLP). Rejection happens when the upstream port has TLPs queued, when L1 is not enabled, or when the port has DLLPs (ACK/NAK) pending transmission. After a NAK, the downstream device falls back to L0s if possible.

Software-initiated L1 entry (D-state change)

When software writes a non-D0 power state to the device’s PMCSR Power State field [1:0], the device transitions its link to L1 using a similar but slightly different DLLP: PM_Enter_L1. This is sent to the upstream device, which responds with PM_Request_ACK. The handshake then follows the same EIOS sequence as ASPM L1 entry.

▶ L1 Exit Protocol

Either the upstream or downstream side can initiate L1 exit. No negotiation is needed — exit is unilateral. The initiating side simply exits electrical idle and sends TS1 ordered sets. The link partner detects the exit from electrical idle and responds with TS1s. Both sides then follow the Recovery LTSSM substates (Recovery.RcvrLock → Recovery.RcvrCfg → Recovery.Idle) before returning to L0.

Switch propagation rule: 1 µs. When a switch port detects L1 exit from a downstream device, it must exit L1 on its upstream link within 1 µs. Similarly, when it detects L1 exit from its upstream link, it must exit L1 on all downstream ports that are in L1 ASPM within 1 µs. This cascaded wake prevents accumulated latency across multi-switch topologies. The switch does not wait for the downstream link to fully reach L0 before starting the upstream exit.

📋 L1.1 and L1.2 Sub-States

L1 sub-states extend L1 with progressively deeper power savings by removing the reference clock and PLL. They are defined in the L1 PM Sub-States extended capability (Cap ID 001Eh, covered in PCIe-22).

Figure 4 — L1 sub-states. Standard L1 keeps the reference clock running. L1.1 removes the reference clock but keeps PLLs on (using internal clocking). L1.2 goes furthest — PLLs are turned off, achieving maximum power savings at the cost of PLL re-lock time on exit (typically hundreds of microseconds to milliseconds). L1.2 entry is gated by LTR tolerance reporting to prevent entering it when the device needs low latency.

Sub-state	Ref clock	PLL state	Common mode	Exit latency	Control method
Standard L1	On	Locked	May remain	2–100 µs	ASPM or D-state
L1.1 (ASPM)	Off	On (internal)	Removed	Tens of µs + Recovery	ASPM
L1.1 (PM)	Off	On (internal)	Removed	Tens of µs + Recovery	Software D-state
L1.2 (ASPM)	Off	Off	Removed	T_POWER_ON + Recovery (100s µs–ms)	ASPM + LTR gate
L1.2 (PM)	Off	Off	Removed	T_POWER_ON + Recovery	Software D3hot

⚡ L0p — Low-Power Active (Gen 6 New)

L0p is an entirely new link power state introduced in PCIe 6.0. It addresses a fundamental problem unique to Gen 6’s PAM4 signalling at 64 GT/s: idle gaps between bursts of traffic are common (AI accelerators, for example, have intense computation phases followed by communication bursts), but the overhead of entering L1 (Recovery exit, TS1/TS2 exchange) is too large for the short idle windows between bursts.

L0p is not an out-of-band idle state like L0s or L1. It is an in-band active state operating within the L0 domain — the link never leaves L0 technically, but power is reduced by operating at a reduced configuration:

Figure 5 — L0p vs L0 full. In L0p, the link remains in its L0 trained state (no LTSSM state change) but operates at reduced resource consumption — either fewer active lanes, reduced FEC processing, or reduced modulation complexity. Because the link is still trained and the LTSSM is in L0, returning to full L0 capacity takes sub-microsecond time. This is dramatically faster than L0s (which requires N_FTS sequences) or L1 (which requires full Recovery).

L0p mechanism details

L0p operates through flit-mode bandwidth reduction specific to Gen 6’s flit-based Transport Layer. Two primary power reduction mechanisms exist:

Lane scaling: a Gen 6 x16 link in L0p may operate at x8 or x4 — the unused lanes are put into a low-power standby while the link remains in L0. TLPs continue to flow on the active lanes. When the device needs full bandwidth, it negotiates back to x16 without entering Recovery — the unused lanes “wake up” within the flit synchronisation window.
FEC compression: Gen 6 uses forward error correction (Reed-Solomon FEC) at the flit level. In L0p, FEC overhead can be reduced by modifying the coding rate, reducing the computational power required by the FEC encoder/decoder on each lane.

L0p entry and exit are negotiated using new Gen 6 Ordered Sets (defined in the PCIe 6.0 spec, not available in older specifications). The Physical Layer 64.0 GT/s Extended Capability (Extended Cap ID 002Ch) reports L0p capability and current operating configuration.

L0p is the Gen 6 answer to AI inference latency. An H100 or MI300X GPU performing matrix multiplication generates bursts of PCIe traffic (DMA writes to system memory) separated by periods of GPU-internal computation. In Gen 5, these idle gaps force the link to remain in full L0 (wasting power) or enter L0s/L1 (incurring wake latency). Gen 6 L0p provides a middle ground: cut lane count from x16 to x4 during the idle gap (saving ~75% of lane power), then return to x16 in sub-microsecond time when the next DMA burst is ready. This matters enormously for power-capped data centres running hundreds of GPUs.

Mechanism	L0s	L1	L0p (Gen 6)
Link state	L0s (out of L0)	L1 (out of L0)	Still in L0
LTSSM transition	Yes (EIOS → EI)	Yes (DLLP + EIOS)	No
Exit mechanism	N_FTS + SOS	Recovery (TS1/TS2)	L0p ordered set negotiation
Exit latency	100 ns – 1 µs	2 – 100+ µs	Sub-microsecond
Both directions affected	One direction only	Yes	Yes (coordinated)
Generation	Gen 1+	Gen 1+	Gen 6 only
Primary use case	Light idle periods	Deep idle, D-state changes	GPU/AI burst gaps at 64 GT/s

📋 L2 and L3 — Power Removed

L2 and L3 are not ASPM states — they require an explicit OS-initiated power-down sequence. They represent conditions where main power has been removed from the device. The spec calls them pseudo-states because the LTSSM is not operational once power is removed.

State	Main power	Vaux (3.3V standby)	Communication	Wake mechanism	Recovery
L2	Off	Present	None (clock off)	Beacon or WAKE# signal	Fundamental reset + re-enumeration
L3	Off	Off	None	Physical power-on only	Fundamental reset + re-enumeration

L2 (Auxiliary power) — the device retains Vaux (3.3V standby rail) but main power is removed. A device in L2 can monitor for wake events and signal a wakeup to the system by asserting a Beacon signal on the PCIe lane or an out-of-band WAKE# sideband signal. The Root Complex detects this and initiates power restoration and re-enumeration.

L3 (No power) — all power is removed including Vaux. The device has no means to communicate or detect events. Recovery requires restoring all power supplies, asserting PERST# reset, and running the full boot-time enumeration sequence again. L3 corresponds to what happens when a user presses the physical power button for a hard-off.

▶ L2/L3 Ready Handshake

Before power can safely be removed, all devices must acknowledge that they are ready. The OS power manager initiates the following sequence:

Software places all functions in the PCIe fabric into D3hot state. All devices enter L1 as required by the D3hot transition.
Software sends a PME_Turn_Off broadcast Message TLP from the Root Complex. This tells all devices to disable their PME generation capability — preventing PME messages from being lost during power removal. Delivery of PME_Turn_Off brings each link back to L0 temporarily as it propagates downstream.
Every device acknowledges by returning a PME_TO_ACK Message TLP upstream. Switches aggregate the ACKs from all downstream ports and forward one PME_TO_ACK upstream per port.
After sending PME_TO_ACK, each device repeatedly sends PM_Enter_L23 DLLP to its upstream port until it receives PM_Request_ACK DLLP back. The device then sends EIOS and enters electrical idle.
Switches wait until all downstream ports have entered L2/L3 Ready before sending PM_Enter_L23 upstream. This bottom-up order ensures no device sends a PME message after the Root Complex has powered off.
The reference clock and main power can be removed not sooner than 100 ns after all links have entered the L2/L3 Ready state.

L2/L3 Ready is a transitional state, not a steady state. L2/L3 Ready means “I am ready for power to be removed.” Once power is actually removed, the state becomes L2 (Vaux present) or L3 (no power). The 100 ns minimum wait between observing L2/L3 Ready on all links and removing power gives devices time to complete any in-flight operations.

📋 ASPM Configuration Registers

ASPM is controlled through two registers in the PCIe Capability structure (PCIe Cap ID 10h, covered in PCIe-21):

Figure 6 — ASPM registers. Link Capabilities bits [11:10] (ASPM Support) is hardwired by the device designer and tells software what the device supports. Link Control bits [1:0] (ASPM Control) is writable by software to enable or disable ASPM independently. Both devices at each end of a link have these registers — enabling ASPM on one side without enabling it on the other is incorrect and will cause unstable behaviour.

ASPM must be enabled on both sides of the link. If software enables L1 in the endpoint’s Link Control register but not in the Root Port’s Link Control register, the endpoint will attempt to enter L1 but the Root Port will reject it (PM_Active_State_NAK). The device will loop between L0s and failed L1 entry attempts, wasting power and causing potential instability. Always configure ASPM in pairs — endpoint and its Root Port, or switch Upstream Port and its downstream-facing Root Port.

📋 Exit Latency Registers

Register	Location	Content
L0s Exit Latency	Link Capabilities [14:12]	Maximum time from L0s exit initiation to L0. 3-bit field, 8 values from <64ns to >4µs. Updated after Common Clock Configuration change + Retrain Link.
L1 Exit Latency	Link Capabilities [17:15]	Maximum time from L1 exit initiation to L0. 3-bit field, 8 values from <1µs to >64µs. Includes Recovery state time.
Acceptable L0s Latency	Device Capabilities [8:6]	Maximum L0s exit latency the endpoint can tolerate before its performance degrades. 3-bit, same encoding. Software compares this with path L0s latency sum.
Acceptable L1 Latency	Device Capabilities [11:9]	Maximum L1 exit latency the endpoint can tolerate. 3-bit, values from <1µs to unlimited. Software compares this with path L1 latency sum.
Common Clock Configuration	Link Control bit 6	When 1: both sides share the platform reference clock. Reduces L0s exit latency (fewer FTS needed). Triggers Retrain Link to update N_FTS values.
Slot Clock Configuration	Link Status bit 11	Hardware reports whether device uses the platform clock (1) or an independent clock source (0). Software reads both ends to determine if Common Clock Configuration can be set.

📋 ASPM Policy — How Software Decides

Software cannot blindly enable ASPM on every link. If the total exit latency across the path from an endpoint to the Root Complex exceeds the endpoint’s acceptable latency, ASPM will cause performance degradation — the device will run out of its internal buffers waiting for the link to return to L0. Software must calculate whether enabling ASPM is safe for each endpoint:

Figure 7 — ASPM path latency calculation. Software reads the L1 exit latency of every link in the path (each bridge/switch hop adds its own latency). The worst-case is the maximum link latency in the path (since cascaded exits happen in parallel per the 1µs propagation rule). This is compared with the endpoint’s Acceptable L1 Latency. If the path latency exceeds the endpoint’s tolerance, L1 must be disabled for that endpoint.

The latency calculation is done independently for L0s and L1. It is common to enable L1 for a device even though L0s is disabled (or vice versa), depending on the path latency calculation results. BIOS typically performs this calculation during POST and programs ASPM appropriately. The OS power manager may later re-evaluate and adjust ASPM settings based on performance profiling.

📋 Software-Initiated Link PM (D-State → L1)

When software writes to the PMCSR Power State field to place a device in D1, D2, or D3hot, the device must autonomously initiate an L1 transition. This happens without ASPM being enabled — it is a mandatory requirement for any D-state change below D0:

Device D-state	Required link state	Entry DLLP	Exit trigger
D0	L0 (fully operational)	None	N/A
D1	L1 (mandatory)	PM_Enter_L1	Software config write to PMCSR (D0 return) or PME event
D2	L1 (mandatory)	PM_Enter_L1	Software config write or PME event
D3hot	L1 (mandatory)	PM_Enter_L1	Software config write or PME event
D3cold	L2 or L3 (after L2/L3 Ready handshake)	PM_Enter_L23	Power restore + fundamental reset

The L1 entry for D-state changes uses the same 11-step handshake as ASPM L1 but uses the PM_Enter_L1 DLLP (a different DLLP type from the ASPM request). Software does not directly control the timing of L1 entry — after writing the PMCSR register, the hardware handles the entire DLLP negotiation and electrical idle sequence autonomously.

⚡ Power Management in Gen 6

All legacy link states (L0, L0s, L1, L1.1, L1.2, L2, L3) and their protocols (EIOS, PM_Enter_L1, PM_Request_ACK, PME_Turn_Off, N_FTS, ASPM Control register) are fully preserved in Gen 6. A Gen 6 link can use all the same power states as a Gen 3 link — backward compatibility is complete.

Feature	Gen 6 change
L0, L0s, L1, L1.1, L1.2, L2, L3	Unchanged — same protocols, same DLLP types, same ASPM register layout
L0p	New in Gen 6. In-band bandwidth reduction within L0. Sub-µs exit latency. PAM4-specific.
EIOS for L0s	Gen 6 PAM4 uses a new EIOS block format for 64b/66b flit encoding — different bytes from Gen 3 128b/130b EIOS, but same conceptual role.
N_FTS for L0s exit	Gen 6 PAM4 requires more FTS sequences for clock recovery than Gen 3 NRZ — PAM4’s 4-level eye is harder to re-lock. N_FTS values will be larger.
ASPM Control register	Unchanged — same bits, same encoding. L0p is NOT controlled via ASPM Control; it uses the Physical Layer 64.0 GT/s capability (002Ch).
L1 exit latency	Gen 6 PHY relock from L1 may be longer than Gen 3 due to PAM4 equalization requirements. Devices must report accurate L1 exit latency in Link Capabilities.
CXL.io power management	CXL.io uses standard PCIe link power management. CXL.cache and CXL.mem have their own protocol-level quiesce sequences that must complete before L1 entry.

L0p is the defining Gen 6 PM innovation. At 64 GT/s, even L0s carries significant penalty — the N_FTS count is higher due to PAM4 re-lock complexity, making L0s exit latency worse than at Gen 3. L0p avoids this penalty entirely by never leaving the L0 domain. For AI workloads with bursty traffic patterns (the dominant use case for Gen 6), L0p delivers the power savings of L0s with a latency profile closer to L0 itself.

📋 Quick Reference

State	Ref clock	PLL	Both Tx idle	Exit latency	Control	Entry trigger
L0	On	Locked	No	N/A	—	Normal operation
L0p (Gen 6)	On	Locked	No (reduced)	<1 µs	HW (ASPM-like)	Burst gap at 64 GT/s
L0s	On	Locked	One direction	64 ns – >4 µs	HW (ASPM)	Tx inactivity timeout
L1	On	Locked	Yes	2–100 µs	HW (ASPM) or SW	DLLP negotiation or D-state
L1.1	Off	On	Yes	Tens of µs	HW (L1SS ASPM)	L1 + clock removal
L1.2	Off	Off	Yes	100 µs – ms	HW (L1SS ASPM + LTR gate)	L1.1 + PLL shutdown
L2	Off	Off	Yes	Full re-init	SW only	L2/L3 Ready handshake + Vaux
L3	Off	Off	Yes	Full re-init	SW only	L2/L3 Ready handshake + no Vaux

Item	Value / Rule
L0s entry	Tx sends EIOS, enters EI within 8 ns. No negotiation. Local decision.
L0s exit	Tx sends N_FTS FTS ordered sets then SOS (8b/10b) or EIEOS+SDS (128b/130b). Rx re-locks CDR.
L0s → L1 direct path	Not allowed. Must return to L0 first, then enter L1.
L1 ASPM entry DLLP	PM_Active_State_Request_L1 (downstream → upstream). Reply: PM_Request_ACK or PM_Active_State_NAK.
L1 SW entry DLLP	PM_Enter_L1 (device → upstream). Reply: PM_Request_ACK. Both: then EIOS + EI.
L1 exit	Either side exits EI, sends TS1s. Recovery state (TS1/TS2 exchange) → L0.
Switch L1 exit propagation	Within 1 µs of detecting downstream L1 exit, switch exits L1 on upstream link. Parallel, not sequential.
L1.2 gate	LTR_L1.2_THRESHOLD in L1SS Control 1. L1.2 only entered if current LTR value exceeds this threshold.
ASPM Control register	Link Control bits [1:0]: 00b=disabled · 01b=L0s · 10b=L1 · 11b=both. Must match on both ends of link.
ASPM Support register	Link Capabilities bits [11:10]: 00b=none · 01b=L0s · 10b=L1 · 11b=both. Read-only.
Common Clock Config	Link Control bit 6. Shortens L0s exit latency. Requires Retrain Link to update N_FTS.
L0s Acceptable Latency	Device Capabilities [8:6]. SW compares with max path L0s latency — disables ASPM L0s if path exceeds tolerance.
L1 Acceptable Latency	Device Capabilities [11:9]. SW compares with max path L1 latency — disables ASPM L1 if path exceeds tolerance.
D-state → link state	D0→L0. D1/D2/D3hot→L1 (mandatory). D3cold→L2/L3 (after handshake).
L2/L3 Ready sequence	Software D3 → PME_Turn_Off broadcast → PME_TO_ACK from all → PM_Enter_L23 DLLP → EI → power off ≥100 ns later.
L0p (Gen 6)	In-band bandwidth reduction within L0. Lane scaling or FEC reduction. Sub-µs exit. Controlled via PHY 64.0 GT/s Extended Cap (002Ch). Not via ASPM Control bits.