In Lecture 12, we introduced the concept of Quality of Service (QoS) and Differentiated Services. But how does the PCIe fabric actually distinguish between high-priority packets and normal background traffic?
In Lecture 13, we explore the software and hardware combination that makes QoS possible: Traffic Classes (TC) and Virtual Channels (VC).
Part 1: Traffic Classes (TC) – The Software Labels
To differentiate traffic and establish priority, PCIe uses Traffic Classes. Software assigns an 8-level priority to packets using a 3-bit TC field located in the Transaction Layer Packet (TLP) header, ranging from TC0 (lowest) to TC7 (highest).
During system initialization, a device driver communicates its required service levels to the system’s management software (such as an Isochronous Broker), which then dictates the appropriate TC values the device should use.
- The TC0 Default: TC0 is the default class. If configuration software is unaware of PCIe QoS features, it will default to using TC0 for all transactions.
- Keeping the Fast Lane Clear: To ensure that standard system operations never interfere with high-priority data streams, mundane maintenance-level traffic—specifically Configuration, I/O, and Message transactions—are strictly required to use the default TC0.
Part 2: Virtual Channels (VC) – The Hardware Lanes
If Traffic Classes are the software priority labels attached to a packet, Virtual Channels (VCs) are the physical hardware mechanisms that deliver them. VCs are independent hardware buffers that act as parallel queues for outgoing packets.
Every PCIe port must implement at least the default VC0, but a device can support up to 8 independent VCs (VC0 through VC7).
Think of VCs like a toll road: having multiple VCs is like having dedicated, high-priority fast lanes at a toll booth. If there was only one path, everyone’s data access time would be bottlenecked by the slowest packet. Having multiple independent VC buffers ensures that high-priority traffic is not delayed by slower, lower-priority packets taking up the standard lanes.
Part 3: TC-to-VC Mapping – Connecting Priority to Hardware
The TC value assigned to a packet travels completely unchanged from its original source all the way to its final destination. However, as the packet traverses the fabric, the TC must be specifically mapped to an available VC at every individual Link along the way.
Configuration software sets up this association using the 8-bit TC/VC Map field located in the VC Resource Control Register. In this field, each bit position represents a corresponding TC value (bit 0 = TC0, bit 1 = TC1, etc.), allowing software to dictate exactly which hardware buffer handles which priority label.
Software has a great deal of flexibility when doing this, but it must adhere to a few strict rules:
- Identical Configurations: The TC/VC mapping configuration must be perfectly identical for the two ports attached on either end of the same Link.
- The Default Path: TC0 is automatically mapped to VC0.
- No Splitting: While a single VC hardware buffer can be configured to handle multiple different TCs, a single TC may not be mapped to more than one VC.
To determine how many VCs to actually use on a Link, configuration software reads the Extended VC Count field to check the maximum capabilities of the devices on both ends, typically assigning the highest common number of supported VCs.