In PCI Express, high-level transactions originate in the device core of the transmitting device and terminate at the core of the receiving device. The Transaction Layer acts on these requests to assemble outbound Transaction Layer Packets (TLPs) at the transmitter and interpret them at the receiver.
Let’s explore the step-by-step flow of how a packet is built, protected, and delivered across the three main layers of the PCIe architecture.
Part 1: TLP Assembly at the Transmitter
Before a packet can be sent across the Link, the transmitting device must assemble it. This happens in a coordinated sequence from the core down to the physical wire:
- Step 1: The Device Core Initiates the Request The core logic of the transmitting device sends a request to its PCIe interface. This request includes essential routing and payload details, such as the target address or ID, the transaction type (e.g., a memory read), the data payload (if any), the Traffic Class to determine priority, and specific transaction attributes like Relaxed Ordering or No Snoop.
- Step 2: The Transaction Layer Builds the Header Based on the core’s request, the Transaction Layer builds the TLP header and appends the data payload. It also optionally calculates and appends an End-to-End CRC (ECRC) digest, which protects the packet’s contents all the way to its final destination. The assembled TLP is then placed into a Virtual Channel buffer, where it waits until the receiver has enough flow control credits to accept it.
- Step 3: The Data Link Layer Adds Link Protection Once the TLP is passed down, the Data Link Layer assigns it a unique Sequence Number and calculates a Link CRC (LCRC). It saves a copy of this complete packet in a local Retry Buffer in case it gets corrupted during transmission and needs to be resent.
- Step 4: The Physical Layer Prepares for Transmission The Physical Layer prepares the packet for the serial wire. It handles byte striping, scrambling, encoding, and serializing the bits. Depending on the PCIe generation, it also adds framing symbols (like the STP token at the start and the END control character at the tail for Gen1/Gen2) to define the absolute boundaries of the packet. The packet is then transmitted across the Link.
Part 2: TLP Disassembly at the Receiver
When the packet arrives at the receiving device, the entire preparation process must be perfectly reversed to check for errors and deliver the data to the target core:
- Step 1: The Physical Layer Reconstructs the Symbol Stream The receiving Physical Layer de-serializes the incoming bit stream, decodes the symbols, and un-stripes the bytes. It removes the physical control framing characters (STP and END) because they only have meaning at the Physical Layer, and then forwards the raw packet to the Data Link Layer.
- Step 2: The Data Link Layer Checks for Link Errors The receiver’s Data Link Layer calculates its own CRC and compares it against the LCRC attached to the packet. If the CRC and Sequence Number match perfectly, the packet is deemed error-free. The layer then removes the Sequence Number and LCRC, passes the TLP up to the Transaction Layer, and returns an Ack (Acknowledge) DLLP to the sender. If an error is detected, a Nak is sent instead, triggering the transmitter to replay the packet from its Retry Buffer.
- Step 3: The Transaction Layer Delivers the Data Finally, the Transaction Layer receives the payload. It decodes the TLP header and passes the transaction information to the core logic for the appropriate action. If this receiving device is the final destination for the packet, it will also perform a final check for ECRC errors and report any issues directly to the core.