Welcome to Part Two of our PCIe course: The Transaction Layer! In this first lecture, we are diving into the fundamentals of the packet-based protocol and how data moves across a PCI Express Link.
Unlike older parallel buses, serial transport buses like PCIe do not rely on side-band control signals to identify what is happening on the Link at any given moment. Instead, the bit stream must have a recognizable format. Information moves across an active PCIe Link in fundamental chunks called packets, which are composed of symbols.
The two major classes of packets exchanged on the link are high-level Transaction Layer Packets (TLPs) and low-level Link maintenance packets called Data Link Layer Packets (DLLPs).
Switching to a packet-based protocol brings three distinct advantages for data integrity and system reliability:
1. Packet Formats Are Well-Defined
Older buses like PCI allowed transfers of indeterminate sizes, making it impossible to identify the boundaries of a payload until the transfer actually ended. Furthermore, either device could terminate the transfer before it completed, making it difficult to calculate a checksum over the entire payload.
By comparison, PCIe packets have a known size and a highly structured format. Every packet features a header at the beginning that indicates the packet type and contains all required and optional fields. Once a packet transfer begins, the recipient cannot pause or terminate it early, allowing the protocol to securely include framing symbols, a Sequence Number, and CRC data to aid in reliable delivery.
2. Framing Symbols Define Packet Boundaries
For Gen1 and Gen2 modes of operation (which use 8b/10b encoding), each TLP and DLLP is framed by Start and End control symbols. This clearly defines the absolute boundaries of the packet for the receiver.
This is a massive improvement over older standards like PCI and PCI-X, where the assertion and de-assertion of a single signal (FRAME#) indicated the start and end of a transaction. In those older systems, a simple glitch on a control signal could cause the target to completely misconstrue bus events. Because a PCIe receiver must properly decode a complete 10-bit symbol, unexpected or unrecognized symbols are easily caught and handled as errors. (Note: Gen3 operation uses 128b/130b encoding, replacing traditional control characters with an STP token that contains packet size information).
3. In-Band CRC Protects the Entire Packet
Legacy PCI systems relied on simple side-band parity signals during address and data phases. PCIe completely replaces this with an in-band Cyclic Redundancy Check (CRC) value that verifies the error-free delivery of the entire packet.
To take this protection a step further, the transmitter’s Data Link Layer appends a unique Sequence Number to every TLP. The transmitter maintains a copy of each sent TLP in a local Retry Buffer until it is officially acknowledged by the receiver. This forms the basis of the Ack/Nak Protocol—an ingenious error recovery mechanism that ensures if a receiver detects a CRC error, the corrupted packet can be automatically resent, resolving the error right at the Link where it occurred.