Welcome to Lecture 3 of the Transaction Layer series! Now that we understand how Transaction Layer Packets (TLPs) are assembled and disassembled, it is time to open them up and examine their core structural component: the header.
Regardless of the specific transaction, every PCIe packet begins with a highly structured header that dictates how the packet will be treated as it travels across the fabric. A TLP header can be either 3 Double Words (3DW) or 4 Double Words (4DW) in size, meaning it takes up 12 or 16 bytes respectively.
Let’s dive into the essential fields common to nearly all generic TLP headers:
1. Format (Fmt) Field
Located in Byte 0 (Bits 7:5), this critical 3-bit field tells the receiver two key pieces of information: the size of the header (3DW or 4DW) and whether or not a data payload is attached. The encodings are straightforward:
- 000b: 3DW header, no data payload
- 001b: 4DW header, no data payload
- 010b: 3DW header, with data payload
- 011b: 4DW header, with data payload
Note: For memory requests, an address that falls below the 4GB boundary must use a 3DW header.
2. Type Field
Right next to the Fmt field is the 5-bit Type field (Byte 0, Bits 4:0). The Type field works directly with the Format field to define the exact transaction variant being used, such as a Memory Read Request, IO Write Request, Configuration Request, or a Completion,,. Together, Fmt and Type dictate exactly how the rest of the header bytes should be interpreted.
3. Traffic Class (TC)
Found in Byte 1 (Bits 6:4), this 3-bit field is the foundation for PCIe’s Quality of Service (QoS). It allows software to encode an 8-level priority to the packet, ranging from TC0 to TC7. TC0 is the default class, while TC1 through TC7 are used to provide differentiated, prioritized services for traffic like streaming video. Any completion associated with a request will inherit the same TC value.
4. Attributes (Attr)
The transaction attributes provide hints to the system hardware on how to optimize the packet’s delivery. These bits are split up in the header:
- Relaxed Ordering (Bit 5): When set to 1, this enables PCI-X relaxed ordering, permitting switches in the fabric to reorder transactions to maximize performance.
- No Snoop (Bit 4): When set to 1, the requester guarantees that there are no host cache coherency issues for this transaction. This saves the system valuable time because it can safely skip the normal processor cache snoop.
- ID-Based Ordering (IDO) (Bit 2): This bit indicates whether ID-based ordering is to be used, allowing the fabric to further reorder packets originating from completely unrelated requesters to prevent stalls.
5. Length Field
Located across Byte 2 (Bits 1:0) and Byte 3 (Bits 7:0), this 10-bit field simply indicates the size of the data payload being transferred in Double Words (DW). The transfer size can range from just 1 DW (encoded as 00 0000 0001b) all the way up to the maximum 1024 DW, which equates to 4KB (encoded as all zeros: 00 0000 0000b). If the Length field does not match the actual amount of data transferred, the receiver treats it as a Malformed TLP.
6. TD Bit and End-to-End CRC (ECRC) Digest
To ensure flawless data integrity from the originating core to the final destination, PCIe utilizes an End-to-End CRC (ECRC) Digest.
- The TLP Digest (TD) Bit: Located at Byte 2, Bit 7, this bit alerts the receiver that an optional 4-byte (1 DW) ECRC Digest has been appended to the very end of the packet,.
- How ECRC Works: While standard Link CRC checks for errors across a single physical link, the ECRC travels forward completely unchanged. It covers all fields within the TLP that do not legally change as the packet navigates across the fabric,. When the ultimate target device checks this ECRC, it can detect any internal corruption that might have occurred inside a Switch or Root Complex along the way.
Important Rule: If a receiver sees that TD=1 but cannot locate the actual Digest at the end, the packet is instantly flagged as a Malformed TLP.