When exploring the PCI Express (PCIe) Data Link Layer, one of the most important concepts to master is the physical structure of its primary messenger: the Data Link Layer Packet (DLLP). Unlike standard data packets, DLLPs are strictly engineered for high-speed, localized link management.
Here is a breakdown of the physical anatomy and core characteristics that make DLLPs so efficient.
A Strict 8-Byte Limit
To ensure that link management remains incredibly fast and unobtrusive, Data Link Layer Packets are always exactly 8 bytes long. This fixed size applies universally, regardless of whether the system is using Gen1/Gen2 8b/10b encoding or Gen3 128b/130b encoding.
The “No Data Payload” Rule
Perhaps the most striking characteristic of a DLLP is what it lacks. There is never a data payload attached to a DLLP. Because these packets are used strictly for localized Link housekeeping—such as Ack/Nak signaling, power management, and flow control—all necessary communication is compressed directly into the packet’s core without the need for a bulky data payload.
Inside the 8 Bytes: The Physical Anatomy
Every 8-byte DLLP is neatly divided into three distinct functional components:
1. The 4-Byte Core (The Message) This 1 Double Word (DW) section holds the actual communication information. It contains:
- A 1-byte DLLP Type field, which identifies the packet’s purpose (for example, identifying it as an Ack, Nak, or Power Management request).
- 3 additional bytes of attributes, which vary depending on the specific DLLP type.
2. The 16-bit CRC (2 Bytes of Protection) To protect the packet’s contents during transit, a 2-byte Cyclic Redundancy Check (CRC) is calculated based on the 4-byte core and appended directly after it. It is important to note that this 16-bit CRC is strictly for the DLLP; it is smaller and calculated differently than the 32-bit LCRC used to protect Transaction Layer Packets (TLPs).
3. The Framing Symbols (2 Bytes of Boundaries) The final two bytes of the DLLP’s footprint are used for framing so the physical receiver can easily identify the packet’s boundaries. How this framing is applied depends on the PCIe generation:
- Gen1 and Gen2 mode (8b/10b encoding): A 1-byte Start of DLLP (SDP) symbol is added to the beginning of the packet, and a 1-byte End Good (END) symbol is added to the end.
- Gen3 mode (128b/130b encoding): A 2-byte SDP Token is added to the very front of the packet to complete the 8-byte size, and no END symbol is required at the tail.
Summary
The anatomy of a DLLP is a masterclass in hardware efficiency. By adhering to a strict, 8-byte fixed size that entirely omits a data payload, the Data Link Layer can continuously and reliably exchange critical link health and flow control metrics without ever causing congestion on the main data pathways.