Q 0.6: Message Requests – Replacing Physical Pins with “Virtual Wires”

In earlier generations of computer buses, like legacy PCI and PCI-X, system functions such as interrupts, error reporting, and power management required dedicated physical wires (known as sideband signals) to be routed across the motherboard.

PCI Express takes a radically different approach. To reduce pin counts and simplify board routing, PCIe replaces these physical sideband signals with Message Requests. These packets act as “virtual wires,” simulating the exact behavior of physical pins through in-band data packets.

All Message Requests use a 4 Double Word (4DW) header format and are handled very much like posted Memory Write transactions, meaning they do not require Completions.

Let’s explore four vital categories of Message Requests that keep a PCIe system running smoothly:

1. INTx Interrupt Signaling

While modern PCIe devices primarily use Message Signaled Interrupts (MSI), older legacy devices still rely on the traditional PCI interrupt pins (INTA, INTB, INTC, and INTD). PCIe supports these legacy devices by simulating the physical pins using an ingenious “virtual wire” alternative.

• The Protocol: When a device needs to trigger an interrupt, it sends an Assert_INTx message to the upstream device. Once the software successfully services the interrupt, the interrupting device sends a corresponding Deassert_INTx message to communicate that the virtual signal has been released.
• Strict Rules: INTx messages never contain a data payload (the Length field is reserved) and they are strictly required to use the default Traffic Class (TC0) to ensure predictable delivery.

2. Power Management Messages

PCI Express seamlessly integrates with legacy PCI power management while adding its own hardware-based Link power management. Instead of a physical “wake” or “sleep” pin, PCIe coordinates power states using specific messages:

• PM_Turn_Off: This message is broadcast downstream from the Root Complex to tell all endpoints to prepare for a sleep state.
• PME_TO_Ack: Once an endpoint is ready to transition to the sleep state, it sends this acknowledgment upstream.
• PM_PME: If a sleeping component needs to wake the system up (a Power Management Event), it sends this message upstream to the Root Complex.
• Note: Like INTx, Power Management Messages do not have a data payload and must use TC0.

3. Error Signaling Messages

When a PCIe component detects an error, it doesn’t assert a physical error pin. Instead, it sends an Error Message upstream, which is implicitly routed directly to the Root Complex. The Root Complex then converts these messages into system-specific events so software can react. To help the system diagnose the issue, the message header includes the Requester ID of the agent that detected the fault. Errors are categorized into three distinct message types based on severity:

• ERR_COR: Correctable errors.
• ERR_NONFATAL: Uncorrectable, but non-fatal errors.
• ERR_FATAL: Uncorrectable and fatal errors.

4. Vendor-Defined Messages

The PCIe specification is designed to be future-proof. To allow device manufacturers to expand messaging capabilities beyond the official specification, PCIe supports Vendor-Defined Messages.

• These messages are distinguished by a specific Vendor ID field in the header, and unlike many other message types, they may optionally include a data payload.
• There are two variants: Type 0 and Type 1. If a receiver does not recognize a Type 1 message, it simply discards it silently. However, if it fails to recognize a Type 0 message, it must treat the packet as an Unsupported Request error.