Verilog Designs — Single Port RAM 128×8 — VLSI Trainers Verilog Designs · Module 34 Single Port RAM — 128×8 Complete single-port synchronous RAM designs — synchronous write / synchronous read, synchronous write / asynchronous read, read-first and write-first modes, and byte-enable parameterised RAM — with timing diagrams, function tables, and an exhaustive self-checking testbench […]
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Verilog Designs — 4-bit LFSR — VLSI Trainers Verilog Designs · Module 33 4-bit LFSR Complete Linear Feedback Shift Register designs — Fibonacci (external feedback) LFSR, Galois (internal feedback) LFSR, parametrised N-bit LFSR, and a PRBS (pseudo-random bit sequence) generator — with full 15-state sequence tables, tap polynomial derivation, circuit diagrams, and an exhaustive self-checking
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Verilog Designs — N-bit Universal Shift Register — VLSI Trainers Verilog Designs · Module 32 N-bit Universal Shift Register Complete parameterised N-bit universal shift register with all four modes — hold, shift-right, shift-left, parallel load — plus three variants: arithmetic shift (sign-preserving), rotate (circular shift), and a generate-based structural implementation. Exhaustive testbench verifies every mode
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Verilog Designs — PIPO Shift Register — VLSI Trainers Verilog Designs · Module 31 PIPO Shift Register Complete Parallel-In Parallel-Out (PIPO) shift register — four implementations: basic 4-bit, with clock enable, bidirectional, and universal (all four shift register modes in one) — with function tables, circuit diagrams, waveforms, and an exhaustive self-checking testbench. Contents Introduction
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Verilog Designs — Up-Down Counter — VLSI Trainers Verilog Designs · Module 30 Up-Down Counter Four implementations of a synchronous up-down counter — basic 4-bit, with synchronous load, parameterised N-bit, and Gray-code variant — with function tables, count sequences, waveforms, and an exhaustive self-checking testbench covering reset, up-count, overflow, hold, underflow, down-count, direction change, and
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Verilog Designs — Clock Divider — VLSI Trainers Verilog Designs · Module 29 Clock Divider Four clock divider implementations — divide-by-2 (single toggle flip-flop), divide-by-N even (counter, 50% duty cycle), divide-by-N odd (dual-edge, true 50%), and fractional divider (half-integer) — with circuit diagrams, waveforms, and a testbench that measures period and duty cycle of each
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Verilog Designs — Binary to Gray Code Conversion — VLSI Trainers Verilog Designs · Module 28 Binary to Gray Code Conversion Complete implementation of the Binary-to-Gray conversion circuit — data flow, behavioral, parameterised generate, and reverse Gray-to-Binary — with full truth table, XOR circuit diagram, and exhaustive testbench covering all 256 input values. 📋 Contents
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Verilog Designs — Count the Number of 1s — VLSI Trainers Verilog Designs · Module 27 Count the Number of 1s Four implementations of the population count (popcount) circuit — combinational loop, sequential serial counter, parallel operator, and tree-adder — with an exhaustive self-checking testbench covering all 256 input values of an 8-bit input. 📋
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Verilog Designs — Sequence Detector 1101 Overlapping (Mealy & Moore) — VLSI Trainers Verilog Designs · Module 26 Sequence Detector — 1101 Mealy Machine & Moore Machine · Overlapping Complete overlapping FSM design for 1101 — after each detection, the FSM reuses the longest suffix of the detected sequence that can start a new match,
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Verilog Designs — Sequence Detector 1101 (Mealy & Moore) — VLSI Trainers Verilog Designs · Module 25 Sequence Detector — 1101 Mealy Machine & Moore Machine · Non-Overlapping Complete FSM design for detecting the binary sequence 1101 — both Mealy and Moore implementations with state diagrams, state tables, Verilog code, and a shared exhaustive testbench
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