Top Verilog codes for practice

CODE:1 Verilog code for flip-flop with a positive-edge clock.

// Verilog code for flip-flop with a positive-edge clock.

module flop (clk, d, q);

input clk, d;
output q;
reg q;

always @(posedge clk)

begin
q <= d;
end

endmodule

CODE:2 Verilog code for flip-flop with a negative-edge clock and asynchronous clear.

//Verilog code for flip-flop with a negative-edge clock and asynchronous clear.

module flop (clk, d, clr, q);

input clk, d, clr;
output q;
reg q;

always @(negedge clk or posedge clr)

begin
if (clr)
q <= 1’b0;
else
q <= d;
end

endmodule

CODE:3 Verilog code for flip-flop with a positive-edge clock and synchronous set.

//Verilog code for flip-flop with a positive-edge clock and synchronous set.

module flop (clk, d, s, q);

input clk, d, s;
output q;
reg q;

always @(posedge clk)

begin
if (s)
q <= 1’b1;
else
q <= d;
end

endmodule

CODE:4 Verilog code for flip-flop with a positive-edge clock and clock enable.

//Verilog code for flip-flop with a positive-edge clock and clock enable

module flop (clk, d, ce, q);

input clk, d, ce;
output q;
reg q;

always @(posedge clk)

begin
if (ce)
q <= d;
end

endmodule

CODE:5 Verilog code for a 4-bit register with a pos-edge clock, asynchronous set and clock enable.

//Verilog code for a 4-bit register with a positive-edge clock,asynchronous set and clock enable.

module flop (clk, d, ce, pre, q);

input clk, ce, pre;
input [3:0] d;
output [3:0] q;
reg [3:0] q;

always @(posedge clk or posedge pre)

begin
if (pre)
q <= 4’b1111;
else if (ce)
q <= d;
end

endmodule

CODE:6 Verilog code for a latch with a positive gate

//Verilog code for a latch with a positive gate.

module latch (g, d, q);

input g, d;
output q;
reg q;

always @(g or d)

begin
if (g)
q <= d;
end

endmodule

CODE:7 Verilog code for a latch with a positive gate and an asynchronous clear.

// Verilog code for a latch with a positive gate and an asynchronous clear.

module latch (g, d, clr, q);

input g, d, clr;
output q;
reg q;

always @(g or d or clr)

begin
if (clr)
q <= 1’b0;
else if (g)
q <= d;
end

endmodule

CODE:8 Verilog code for a 4-bit latch with an inverted gate and an asynchronous preset.

// Verilog code for a 4-bit latch with an inverted gate and an asynchronous preset.

module latch (g, d, pre, q);

input g, pre;
input [3:0] d;
output [3:0] q;
reg [3:0] q;

always @(g or d or pre)

begin
if (pre)
q <= 4’b1111;
else if (~g)
q <= d;
end

endmodule

CODE:9 Verilog code for a tristate element using a combinational process and always block.

// Verilog code for a tristate element using a combinatorial process and always block.

module three_st (t, i, o);

input t, i;
output o;
reg o;

always @(t or i)

begin
if (~t)
o = i;
else
o = 1’bZ;
end

endmodule

CODE:10 Verilog code for a tristate element using a concurrent assignment.

// Verilog code for a tristate element using a concurrent assignment.

module three_st (t, i, o);

input t, i;
output o;

assign o = (~t) ? i: 1’bZ;

endmodule

CODE:11 Verilog code for a 4-bit unsigned up counter with asynchronous clear.

// Verilog code for a 4-bit unsigned up counter with asynchronous clear.

module counter (clk, clr, q);

input clk, clr;
output [3:0] q;
reg [3:0] tmp;

always @(posedge clk or posedge clr)

begin
if (clr)
tmp <= 4’b0000;
else
tmp <= tmp + 1’b1;
end

assign q = tmp;

endmodule