1. What Are Regular Expressions (Regex)?
Regular Expressions (Regex) are text patterns used to search, match, and manipulate strings in a file.
They allow Vi to:
- Find specific signal names or patterns
- Filter simulation errors or warnings
- Modify repetitive code or log lines automatically
Regex is the secret behind Vi’s smart searching — it transforms a plain editor into a mini automation tool.
2. Basic Regex Symbols in Vi
| Symbol | Meaning | Example |
| ^ | Beginning of line | /^module → Matches lines starting with “module” |
| $ | End of line | /endmodule$ → Matches lines ending with “endmodule” |
| . | Any single character | /b.t → Matches bat, bit, bot |
| * | Zero or more of previous character | /clk* → Matches cl, clk, clkkk |
| [abc] | Match any one of a, b, or c | /[ABC]_done |
| [^abc] | Match any character except a, b, or c | /[^abc]data |
| [0-9] | Match any digit 0–9 | /data[0-9] |
| [a-z] | Match lowercase letters | /sig[a-z] |
| [A-Z] | Match uppercase letters | /CLK[A-Z] |
| | | Logical OR (alternation) | /fail|error |
| \. | Literal dot (.) | /version\.1 |
| \* | Literal asterisk (*) | /clk\* |
3. Examples of Regex-Based Search
| Pattern | Matches | Use Case |
| /^set | Lines starting with “set” | Searching constraint commands in .sdc |
| /;$ | Lines ending with “;” | HDL syntax validation |
| /clk[0-9] | clk0, clk1, clk2… | Checking multiple clock nets |
| /reset_n|rst_n | reset_n or rst_n | Finding both reset signals |
| /^// | Commented lines | Filtering config comments |
| /error.*timeout | Lines with both “error” and “timeout” | Debugging simulation failures |
4. Regex in Substitution Commands
Combine regex with substitution for bulk text automation:
Syntax:
:[range]s/pattern/replacement/[options]
Example Description :%s/^#.*// Remove all commented lines starting with # :%s/\s\+$// Remove trailing spaces (cleanup) :%s/clk[0-9]/clk_main/g Rename all clock signals clk0, clk1, etc. to clk_main :%s/FAIL|ERROR/ALERT/g Replace FAIL or ERROR with ALERT
💡 Options:
- g – Apply globally in line
- c – Ask for confirmation before replacing
- i – Ignore case
5. Line Anchors and Word Boundaries
| Symbol | Meaning | Example |
| \< | Start of a word | /\<data\> → matches only full word “data” |
| \> | End of a word | /clk\> → matches clk, not clk_main |
| \s | Space | /\s\+ → matches one or more spaces |
| \S | Non-space | /\S\+ → matches non-space text |
Example:
Replace only full-word rst_n with reset_n:
:%s/\<rst_n\>/reset_n/g
6. Real-World Examples for VLSI Engineers
1. Clean Up Log Files
Remove all lines starting with # or empty lines:
:%s/^#.*//g
:%s/^\s*$//g
2. Extract Simulation Failures
Search for any line with “fail”, “error”, or “timeout”:
/fail\|error\|timeout
3. Rename HDL Signals
:%s/\<data_in\>/data_bus/g
:%s/\<rst_n\>/reset_n/g
4. Align Module Names
Find module declarations only:
/^module
5. Cleanup SDC or Tcl Scripts
Remove trailing semicolons and fix spacing:
:%s/;$//g
:%s/\s\+/ /g
7. Combining Regex with Ranges
Apply substitution to specific line ranges:
:100,200s/^set_input_delay/set_delay/g
Changes text only from line 100 to 200 — ideal for editing large timing files.
8. Multi-Pattern Search Tricks
| Task | Command |
| Search for error or warning | /error|warning |
| Search for “fail” followed by “warn” | /fail.*warn |
| Search for line starting with set and ending with clk | /^set.*clk$/ |
| Search for 3-character signals starting with a | /^a..$/ |
9. Debugging Regex in Vi
You can preview what matches before replacing:
:g/pattern/p
Example:
:g/^module/p
Prints all module declarations in the file — helpful when working with multi-module RTL.
Summary
Regular expressions in Vi make pattern-based editing possible — crucial for:
- Debugging large simulation logs
- Editing massive RTL or constraint files
- Automating repetitive search/replace tasks
Once you master regex, you can edit any file with surgical precision — all from the command line.
