Chapter 5.2 – Transaction Layer Packet (TLP) Basics

1. The Role of the Transaction Layer

The Transaction Layer sits at the top of the PCI Express protocol stack and is responsible for creating, managing, and interpreting packets that describe software-visible operations such as memory reads, writes, configuration accesses, and message deliveries.

Its main responsibilities are:

• Constructing outgoing TLPs with the correct header, payload, and attributes.
  
• Breaking down received TLPs and forwarding them to the proper function.
  
• Maintaining ordering rules and transaction identifiers.
  

Every transaction that software initiates—be it a simple register access or a high-bandwidth DMA—travels through this layer.

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2. TLP Assembly

When a request originates (for example, a memory write from a CPU to a device), the Transaction Layer performs the following steps:

1. Header Creation:
   
   • Builds a request header describing operation type (Memory, I/O, Configuration, or Message).
     
   • Includes the address, transaction ID, attributes, and byte enables.
     
2. Payload Attachment (if applicable):
   
   • Adds a data section when required (e.g., memory write).
     
   • Size can vary up to the negotiated Maximum Payload Size (MPS).
     
3. CRC Calculation (Optional Digest):
   
   • Generates an End-to-End CRC (ECRC) if enabled, to catch corruption not detected by the Data Link Layer’s LCRC.
     
4. Transfer to Data Link Layer:
   
   • The fully assembled TLP is passed downward.
     
   • The Data Link Layer appends a sequence number and LCRC, ensuring reliable delivery.
     

This entire process is called TLP Assembly.

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3. TLP Disassembly

At the receiver’s side (endpoint, switch, or root complex):

1. The Physical Layer deserializes the bitstream into bytes.
   
2. The Data Link Layer validates the LCRC and confirms packet order.
   
3. The Transaction Layer removes the header and ECRC (if present).
   
4. It decodes the operation and delivers it to the appropriate address space or internal function.
   

Errors such as Malformed TLP or Unsupported Request are flagged here, typically triggering an Error Message TLP or Advanced Error Reporting (AER) event.

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4. TLP Structure Overview

A generic TLP has three logical sections:

Section	Purpose	Example Fields
Header	Identifies packet type, source, destination, and control attributes	Format, Type, Traffic Class, Attr, Length, Requester ID, Address
Data Payload	Contains actual transfer data (optional)	Up to MPS bytes
Digest (ECRC)	Optional end-to-end CRC protection	32-bit CRC

💡 Note: The Data Link Layer adds its own 16-bit sequence number and 32-bit LCRC, but those are not part of the Transaction Layer view.

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5. Header Format and Variations

PCI Express defines three primary header formats depending on the transaction type:

1. 3-DW Header (no data): Used for small control or read requests that carry no payload.
   
2. 4-DW Header (no data): Adds a 64-bit address field for high address space.
   
3. 3-DW/4-DW Header (with data): Used when the packet includes a payload (e.g., Memory Write TLP).
   

Each format begins with a Format/Type field, a concise code that allows hardware to instantly identify how to interpret the rest of the header.

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6. Example – Memory Read Request

Let’s trace a simple memory read initiated by a Root Complex:

1. Software requests to read 128 bytes from address 0x8 0000.
   
2. The Transaction Layer creates a Memory Read TLP:
   
   • Header: Format = 3-DW No Data, Type = Memory Read, Length = 128 bytes / 4 = 32 DW.
     
   • Requester ID identifies the root complex.
     
3. TLP passes down the stack and is transmitted.
   
4. The completer (endpoint) later returns a Completion with Data TLP containing the requested data.
   

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7. Error Checking and Reliability

The TLP may optionally include an ECRC (End-to-End CRC).
While the Data Link Layer already ensures hop-by-hop reliability using its own LCRC and Ack/Nak protocol, the ECRC guards the payload across the entire path—especially when traversing multiple switches.
If the destination detects an ECRC mismatch, it reports an ECRC Error via AER without requesting retransmission.

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8. Performance Considerations

• Shorter headers (3-DW) mean less overhead and faster transfers.
  
• Large payloads improve bandwidth utilization but increase latency if retransmission occurs.
  
• Designers must choose MPS and MRRS (Max Payload / Read Request Size) carefully to balance throughput and latency.
  

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NOTES

• Every PCIe transaction is represented by a TLP, the fundamental unit of communication.
  
• TLPs are assembled in the Transaction Layer, protected in the Data Link Layer, and serialized in the Physical Layer.
  
• The structure is modular, scalable, and optimized for high-speed serial transport.