1. Motivation
PCI Express (PCIe) replaces the shared-bus model of PCI with a serial, packet-based interconnect.
Rather than using parallel control and data lines, PCIe organizes every transaction—memory reads/writes, configuration accesses, I/O operations, and messages—into packets that move through a layered architecture.
This design improves:
- Scalability: point-to-point serial links allow multiple devices to operate simultaneously.
- Efficiency: link bandwidth is dynamically allocated instead of time-shared.
- Reliability: error checking is handled per packet, simplifying recovery.
2. How the Packet-Based Approach Works
Each PCIe transaction begins in the Transaction Layer, where request information is encoded into a Transaction Layer Packet (TLP).
That packet is passed downward:
- The Data Link Layer adds sequence and CRC information to ensure reliable delivery.
- The Physical Layer serializes the bits and transmits them over differential lanes.
At the receiver, the process reverses—deserialization, CRC verification, header decoding, and final delivery to the target device.
3. Why Packets Are Used
- Structured Format –
Every packet has a clearly defined header, an optional data payload, and a CRC field.
This makes decoding deterministic and simplifies hardware implementation. - Framing Symbols Define Boundaries –
Ordered-set symbols in the Physical Layer mark where each packet starts and ends, enabling precise alignment even at multi-gigabit rates. - End-to-End Protection –
A 32-bit CRC (called LCRC in the Data Link Layer) protects the packet from transmission errors.
If corruption is detected, the receiver can request a retransmission using the Ack/Nak protocol.
4. Advantages Over Parallel Bus Models
| Aspect | Legacy PCI | PCI Express |
| Signaling | Parallel, 32/64 bits | Serial, differential pairs |
| Synchronization | Shared clock | Embedded clock recovery |
| Arbitration | Central bus arbiter | Point-to-point links |
| Data Integrity | Minimal parity checks | CRC and Replay mechanism |
| Bandwidth Scaling | Limited to bus speed | Linear with lane width (x1, x4, x8, x16) |
5. Example: Memory Write Transaction
- Root Complex creates a TLP header describing the target address and byte enables.
- The header plus data payload forms a Memory Write TLP.
- The Data Link Layer adds a sequence number and LCRC.
- The Physical Layer transmits serialized symbols across lanes.
- The endpoint decodes and delivers data to memory, acknowledging success with an Ack DLLP.
NOTES
- PCIe is a packet-switched, layered protocol, not a shared bus.
- Each packet is self-contained, simplifying routing through switches.
- Robust CRC and acknowledgment mechanisms provide error-free, high-speed communication.
- The same framework scales cleanly from Gen1 (2.5 GT/s) to Gen5 and beyond.