The Road to 64 GT/s
A comprehensive analysis of the evolution from PCIe Gen 1 to Gen 6. Explore the exponential bandwidth growth, the paradigm shift to PAM4 signaling, and the intricate updates to the Link Training and Status State Machine (LTSSM).
Performance Metrics: The Doubling Mantra
PCI Express has maintained a consistent trajectory of doubling bandwidth roughly every three years. This section visualizes the raw transfer rates and aggregate bandwidth across generations. Notice the massive jump at Gen 6, driven by PAM4 signaling.
View Configuration
Gen 6 Highlight
Raw bit rate per lane. Using PAM4, this delivers 256 GB/s in an x16 configuration.
Data Source: PCI-SIG Specifications
Encoding & Signaling Evolution
To achieve higher speeds without unmanageable frequency increases, PCIe evolved its encoding schemes. Gen 1/2 used 8b/10b (20% overhead). Gen 3-5 moved to 128b/130b (<2% overhead). Gen 6 introduces a paradigm shift to PAM4 (Pulse Amplitude Modulation 4-levels) and FLIT (Flow Control Unit) based encoding.
Signal Simulation: NRZ (Gen 1-5)
Non-Return-to-Zero (NRZ) uses 2 voltage levels to send 1 bit per clock cycle. Used in Gen 1 through Gen 5.
Gen 6 Architecture Changes
PAM4 Signaling
Instead of just High/Low, the signal now has 4 distinct voltage levels. This allows sending 2 bits per Unit Interval (UI), effectively doubling the data rate without doubling the Nyquist frequency.
FLIT Mode Encoding
Gen 6 abandons 128b/130b for fixed-size Flow Control Units (FLITs). Real payload efficiency depends on the specific FLIT structure (242B payload + CRC/FEC).
FEC (Forward Error Correction)
PAM4 reduces the signal-to-noise ratio. To compensate for higher Bit Error Rates (BER), Gen 6 mandates light-weight FEC within the FLIT to correct errors without a retry.
LTSSM Explorer
The Link Training and Status State Machine manages the PCIe link. Select a state to view details. Use the Gen Context dropdown to see how specific states evolved in Gen 6.
L0 (Active State)
OperationalThis is the normal operational state where data and control packets are exchanged. The link is fully trained at the negotiated speed and width.
Key Transitions
- → Recovery (on error/retrain)
- → L0s/L1 (Power management)